Large-scale integrated EPROM device
Abstract
Abstract The present invention relates to an electrically programmable nonvolatile memory, the memory points of which are formed by MOS transistors (T11, T12) with a floating gate (23) and which is composed of a network of word lines (LM1) extending along rows, and of bit lines (LB1, LB2) extending along columns. A constant potential line (B), which extends along a column, connects sources (22) of said transistors, is formed by a diffusion of a first type of conductivity, and is intercalated one in two between two bit lines. The drain region (21) of the first type of conductivity of each transistor is extended along a column to form a bit line (LB1, LB2). An insulation zone (24) extending along a column is disposed on that side of each bit line which is opposite a constant potential line (B). <IMAGE>
Inventors
- 👤 Albert Bergemont
Bibliographic Details
Claims Analysis
Total Claims: 0References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.