Memory device having a plurality of memory cell arrays with different organization

Abstract

Abstract A memory circuit built into a single-chip integ­ rated circuit includes a first memory cell array (1), and a second memory cell array (2) having a structure different from the structure of the first memory cell array, commonly using part (Ai to Aj) of addresses with the first memory cell array, and having the same number of rows as said first memory cell array. The first and second memory cell arrays are commonly connected to decoding means (3) for decoding the commonly used addresses (Ai to Aj). Each word line (WL) is connected commonly to memory cells (6) of the corresponding row of the first and second memory cell arrays (1, 2). When the potential of a word line is set to the active level, connected memory cells are selected. The decoder is connected to the word lines (WL), to decode the row addresses (Ai to Aj) and set the potential of a word line (WL) corresponding to the row addresses to the active level.

Inventors

• 👤 Kazutaka C/O Intellectual Property Div. Nogami

Bibliographic Details