EP0201185A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1986-03-27
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Granted: —
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Expires: 2006-03-27
Abstract
Abstract @ In a semiconductor memory device, a decoder circuit (1) is located between first (3) and second (5) memory cell arrays. A sequence of driver circuits (121,122...) in the decoder circuit (1) provides driver circuits common to the first and second memory cell arrays. An output terminal (1211 a,1211b,1221a,...) of each driver circuit is connected directly to a data input/output portion (2) for the first memory cell array (3) and connected to another data input/output portion (4) for the second memory cell array (5) via wirings (141 a, 141 b, 142a, ...) traversing the decoder circuit (1 ).
Inventors
- 👤 Kimiaki Sato
- 👤 Yoshihiro Takemae
- 👤 Masao Nakano
- 👤 Nobumi Fujitsu Dai-Go Nakahara-Ryo Kodama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 21:42
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C8/00; G11C8/10; G11C7/00; G11C7/10; G11C7/1006; G11C7/1051; G11C7/12
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
134 words
A semiconductor memory device having a first memory cell array and a first data input/output portion, a second memory cell array and a second data input/output portion, and a decoder circuit between said first and second data input/output portions, said decoder circuit comprising address lines, a sequence of logic gate circuits for receiving address signals and producing selection signals, and a sequence of driver circuits corresponding to said sequence of logic gate circuits for receiving said selection signals and producing drive signals, said sequence of driver circuits being provided as driver circuits common to said first and second memory cell arrays, and the output terminal of each driver circuit being connected directly with said first data input/output portion and being connected with said second data input/output portion through a conductor traversing said decoder circuit.
Claim 2
Dependent Claim
134 words
A semiconductor memory device having a first memory cell array and a first data input/output portion, a second memory cell array and a second data input/output portion, and a decoder circuit between said first and second data input/output portions, said decoder circuit comprising address lines, a sequence of logic gate circuits for receiving address signals and producing selection signals, and a sequence of driver circuits corresponding to said sequence of logic gate circuits for receiving said selection signals and producing drive signals, said sequence of driver circuits being provided as driver circuits common to said first and second memory cell arrays, and the output terminal of each driver circuit being connected directly with said first data input/output portion and being connected with said second data input/output portion through a conductor traversing said decoder circuit.
Claim 3
Dependent Claim
43 words
A device according to claim 1, wherein said first and second memory cell arrays are located at a left side portion and a right side portion respectively, and said decoder circuit is located at a central portion.of said semiconductor memory device. or 2
Claim 4
Independent Claim
25 words
A device according to claim wherein each of said driver circuits corresponds to a respective one of said logic gate circuits. 2 , or 3,
Claim 5
Dependent Claim
24 words
A device according to claim 1, wherein said sequence of driver circuits is located at one side of said sequence of logic gate circuits.
Claim 6
Independent Claim
46 words
A device according to any preceding claim, wherein each said driver circuit comprises two flip-flop circuits connected to respective columns of both memory cells in/said first and second memory cell arrays, wherein in use one of said flip-flop circuits is selected by pre-decoding of address signals.
References Cited (Backward Citations)
No citation records indexed.
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