Patent EP0337109A1 successfully refreshed from Google Patents.
EP0337109A1
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EP
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Method for making contacts
Assignee: International Business Machines Corp
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Filing: 1989-03-08
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Granted: —
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Expires: 2009-03-08
Abstract
Abstract A process for making borderless contacts through an insulating layer to active regions of a semiconductor device is disclosed. After deposition of a silicon nitride layer (18) and an insulation glass layer (20) on a substrate coating semiconductor devices, the contact windows are etched. The windows are etched through the glass layer with BCl₃ etch gases. Next, the windows are etched through the silicon nitride with CH₃F or O₂/CHF₃ gases.
Inventors
- 👤 Jeffrey R. Barber
- 👤 Charles P. Breiten
- 👤 David Stanasolovich
- 👤 Jacob F. Theisen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 04:55
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
105 words
A process for making semiconductor device interconnections comprising the steps of: providing a plurality of semiconductor devices having active regions (12, 14, 16); depositing a diffusion protecting/etch stop layer (18) over said active regions; depositing an insulating layer (20) over said diffusion protection/etch stop layer; depositing a layer of photoresist (22) over said insulating layer; lithographically defining a pattern of contact windows in said photoresist layer (22); etching said pattern of contact windows into said insulating layer (20) with BCl₃; etching said pattern of contact windows into said diffusion protection/etch stop layer (18) with CH₃F or O₂/CHF₃; and depositing at least one electrical interconnection layer.
Claim 2
Dependent Claim
105 words
A process for making semiconductor device interconnections comprising the steps of: providing a plurality of semiconductor devices having active regions (12, 14, 16); depositing a diffusion protecting/etch stop layer (18) over said active regions; depositing an insulating layer (20) over said diffusion protection/etch stop layer; depositing a layer of photoresist (22) over said insulating layer; lithographically defining a pattern of contact windows in said photoresist layer (22); etching said pattern of contact windows into said insulating layer (20) with BCl₃; etching said pattern of contact windows into said diffusion protection/etch stop layer (18) with CH₃F or O₂/CHF₃; and depositing at least one electrical interconnection layer.
Claim 3
Dependent Claim
27 words
The process as claimed in claim 1 with an initial reactive ion step with BCl₃ before etching said pattern of contact windows into said insulating layer (20).
Claim 4
Dependent Claim
23 words
The process as claimed in one of the preceding claims wherein said semiconductor device is an FET having source, drain and gate regions.
Claim 5
Dependent Claim
18 words
The process as claimed in claim 3 wherein said source and drain regions include a layer of silicide.
Claim 6
Dependent Claim
24 words
The process as claimed in claim 4 wherein said silicide is selected from the group consisting of tungsten disilicide, cobalt disilicide, and titanium disilicide.
Claim 7
Dependent Claim
20 words
The process as claimed in one of the preceding claims wherein said diffusion protecting/etch stop layer (18) is silicon nitride.
Claim 8
Dependent Claim
18 words
The process as claimed in one of the preceding claims wherein said insulating layer (20) is borophosphosilicate glass.
References Cited (Backward Citations)
EP0200372A2
Cited
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