EP0200372A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Self-aligned contact window formation in an integrated circuit
Assignee: Thorn EMI North America Inc
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Filing: 1986-04-01
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Granted: —
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Expires: 2006-04-01
Abstract
Abstract A process for self-aligned contact window formation in an integrated circuit leaves a "stick" of etch stop on vertical sidewall surfaces to be protected. The process comprises establishing a layer of oxide (24) over active areas and on top of the gate electrode (14, 16) of a transistor. The oxide (24) is thicker on top of the gate electrode than over the active area. A silicon nitride layer (10) acting as an etch stop is included between the oxide and interlevel dielectric (34) such as BPSG. Contact windows (30,32) may deviate from their intended position and partially overlie a poly edge such as a gate electrode or an isolation (field-shield) or field oxide edge. Two- step etching comprises first etching the BPSG down to the etch stop layer, then etching the etch stop and underlying oxide, leaving a "stick" of etch stop on the side of the layer to be protected. This process preserves for the second step of the etch the differential thickness ratio of the oxide over the gate electrodes as compared to the oxide over the active area. This process allows the simultaneous formation of self-aligned contacts the field oxide, field-shield, and gate electrode edges. It is independent of the type of gate dielectric, gate electrode material, and gate electrode sidewall processing.
Inventors
- 👤 Barbara A. Heath
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 11:23
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10P; H10P14/00; H10P14/40; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10P76/00; H10P76/40
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
71 words
A process of fabricating a contact window in a semiconductor structure with a substrate, intermediate and upper conducting or semiconducting levels, and an interlevel dielectric, the process comprising the steps of: fabricating a partically complete structure having a substrate and an intermediate level; establishing an etch stop on said partially complete structure; adding the interlevel dielectric; positioning contact window locations; and etching through said interlevel dielectric at said contact window locations.
Claim 2
Dependent Claim
71 words
A process of fabricating a contact window in a semiconductor structure with a substrate, intermediate and upper conducting or semiconducting levels, and an interlevel dielectric, the process comprising the steps of: fabricating a partically complete structure having a substrate and an intermediate level; establishing an etch stop on said partially complete structure; adding the interlevel dielectric; positioning contact window locations; and etching through said interlevel dielectric at said contact window locations.
Claim 3
Dependent Claim
92 words
A process as claimed in Claim 1, further comprising etching anisotropically at said contact window locations through said etch stop and underlying insulation to expose an area to which contact is to be made but not entirely through insulation covering an element to which contact is not to be made at the contact window and leaving etch stop on said sidewall surfaces thereof so that the contact window can partially overlie a member to which etec- trical contact is not to be made without causing the circuit being formed to be inoperable.
Claim 4
Dependent Claim
48 words
A process as claimed in Claim 1 or 2, wherein said fabricating step includes providing a dielectric over elements formed from an intermediate level, which dielectric takes longer to etch through entirely than dielectric covering the area to which contact is to be made via the contact window.
Claim 5
Dependent Claim
125 words
A process as claimed in any preceding claim, wherein a contact window is to be made for contact to a source or drain region, wherein the process includes: depositing a polysilicon layer over the substrate and a gate dielectric; defining poly elements in said polysilicon layer; providing a dielectric over said poly elements which takes longer to etch through than dielectric, if any, over the source or drain region to which contact is to be made; establishing said etch stop over said dielectric or over field oxide at least in the region where said contact window will be located; then adding said interlevel dielectric over the semiconductor structure; masking said interlevel dielectric where the contact window is to be formed; then performing said etching steps.
Claim 6
Dependent Claim
27 words
A process as claimed in any preceding claim, wherein said etch stop comprises a layer of material over the top and side of said partially complete structure.
Claim 7
Dependent Claim
18 words
A process as claimed in any preceding claim, wherein said etch stop comprises a layer of silicon nitride.
Claim 8
Dependent Claim
24 words
A process as claimed in Claim 6, wherein said first etching step uses an etching which has a high selectivity of oxide to nitride.
Claim 9
Dependent Claim
24 words
A process as claimed in any preceding claim, wherein said etch stop comprises a dielectric and said etching steps are selective for said dielectric.
Claim 10
Dependent Claim
94 words
A process for forming contacts in a semiconductor structure having a substrate, an intermediate level, and relatively thick interlevel dielectric, the process comprising: establishing an etch stop layer beneath the interlevel dielectric, the etch stop layer covering areas where contact windows are to be made; positioning contact window locaations; and etching at the contact window locations to the etch stop, then etching through the etch stop and underlying materials to open the contact window, leaving etch stop on sidewall surfaces of a member to be protected, whereby the contact window can be self- aligned.
Claim 11
Dependent Claim
94 words
A process for forming contacts in a semiconductor structure having a substrate, an intermediate level, and relatively thick interlevel dielectric, the process comprising: establishing an etch stop layer beneath the interlevel dielectric, the etch stop layer covering areas where contact windows are to be made; positioning contact window locaations; and etching at the contact window locations to the etch stop, then etching through the etch stop and underlying materials to open the contact window, leaving etch stop on sidewall surfaces of a member to be protected, whereby the contact window can be self- aligned.
Claim 12
Dependent Claim
78 words
A process as claimed in Claim 9, further comprising establishing a contact window in a high density semiconductor device having a relatively conductive word line to which contact is not to be made at the contact window and a relatively conductive field-shield edge to which contact is not to be made, said field-shield being covered by a dielectric, and further comprising aligning the contact window to the word line and self-aligning the contact window to the field-shield edge.
References Cited (Backward Citations)
No citation records indexed.
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