Patent EP0318155A1 successfully refreshed from Google Patents.
EP0318155A1
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Forcing synchronisation on two pulse trains
Assignee: International Business Machines Corp
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Filing: 1988-10-26
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Granted: —
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Expires: 2008-10-26
Abstract
Abstract An apparatus and method for digital correction of oscillator drift provides for phase alignment between two clock signals (10, 12) running at nearly the same frequency. Phase alignment is provided by fashioning a delay for one of the clock signals through selection of various lengths (40) of a variable delay path (20) formed from a series of logic circuits. Respective reference signals are derived from the two clocks to be phase-aligned, and the phases of the references are compared in a digital phase comparator (14). The product of phase comparison controls a digital delay selector (18) to generate a sequence of delay signals corresponding to a sequence of detected phase differences. The delay signal sequence controls the variable digital delay. The variable digital delay outputs a corrected clock signal whose phase is aligned with the phase of the other clock signal. The corrected clock signal is used to produce one reference signal, the other reference signal being derived directly from the other clock signal. A second digital phase comparator (22) compares the phase of the corrected clock signal with a predetermined reference phase of the clock signal from which it is derived. When the phases of the clocks are aligned, the second comparator produces a reset signal which resets the digital selection circuit to a predetermined point in the delay signal sequence, thereby operating the variable digital delay to correct the clock signal to a phase corresponding to the predetermined reference phase. The use of digital circuitry to correct for drift between the two clock signals permits the invention to be fully embodied in integrated digital circuits. The elimination of requirement for any analog circuitry to correct for oscillator drift permits phase alignment at various points along the line of clock distribution in an integrated digital system. By use of the invention, phase alignment can be performed on-chip between discreet functions on a single integrated circuit, between separate integrated circuits, and between independently-operating digital systems.
Inventors
- 👤 Michael Joseph Azevedo
- 👤 Charles Anthony Corchero
- 👤 Donald John Lang
- 👤 Gilbert Rouse Woodman, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 22:27
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H04; H04L; H04L7/00; H04L7/0008; H04L7/0012; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
183 words
Apparatus for forcing synchronism on two nominally identical endlessly repetitive pulse trains (CLK) on separate signal paths comprising a limited length string (20) of logic elements selectively insertable in one of the signal paths; first comparator means (14) for comparing the phases of the pulse trains after passage of one of them through the inserted logic elements to test for any phase difference therebetween; control means (16, 18) responsive to the first comparator means for adjusting the number of inserted logic elements by a fixed number thereof if a phase difference is detected; second comparator means (22; 82, 84; 105) for comparing the phases of the pulse trains or derivatives thereof to test for a predetermined phase difference; and reset means responsive to the second comparator means for resetting the control means, if the predetermined phase difference is found, to adjust the number of inserted logic elements directly to a predetermined number thereof, the operation of the control means being independent of any such resetting, whereby the control means operates as if the limited length string of logic elements were of unlimited length.
Claim 2
Dependent Claim
183 words
Apparatus for forcing synchronism on two nominally identical endlessly repetitive pulse trains (CLK) on separate signal paths comprising a limited length string (20) of logic elements selectively insertable in one of the signal paths; first comparator means (14) for comparing the phases of the pulse trains after passage of one of them through the inserted logic elements to test for any phase difference therebetween; control means (16, 18) responsive to the first comparator means for adjusting the number of inserted logic elements by a fixed number thereof if a phase difference is detected; second comparator means (22; 82, 84; 105) for comparing the phases of the pulse trains or derivatives thereof to test for a predetermined phase difference; and reset means responsive to the second comparator means for resetting the control means, if the predetermined phase difference is found, to adjust the number of inserted logic elements directly to a predetermined number thereof, the operation of the control means being independent of any such resetting, whereby the control means operates as if the limited length string of logic elements were of unlimited length.
Claim 3
Dependent Claim
40 words
Apparatus as claimed in claim 1, wherein the second comparator means compares the adjusted pulse train with the other pulse train delayed by a predetermined amount equivalent to from none through one half to all of the available delay elements.
Claim 4
Dependent Claim
74 words
Apparatus as claimed in claim 2, wherein the control means includes means (24) for detecting the sense in which the phases differ and can increase or decrease appropriately the number of inserted delay elements, the second comparator means being arranged to compare after a delay equal to one half of the available delay elements and the resetting means being arranged to reset the number of inserted delay elements to one half of those available.
Claim 5
Dependent Claim
48 words
Apparatus as claimed in claim 2, wherein the second comparator means is arranged to compare at both a null delay and a full delay equal to all the available delay elements and the reset means is arranged to reset to no or all available delay elements inserted appropriately.
Claim 6
Dependent Claim
48 words
Apparatus as claimed in any preceding claim incorporated in a slave unit clocked by a master unit, wherein one pulse train is the clock-in signal from the master unit to the slave unit and the other pulse train is the effective clock signal used by the slave unit.
Claim 7
Dependent Claim
74 words
Apparatus as claimed in any of claims 1 to 4 incorporated in each of a plurality of slave units clocked by a master unit, wherein, in each slave unit, one pulse train is the clock-in signal from the master unit to the slave unit and the other pulse train is the effective clock signal used by the slave unit, whereby synchronism with the master unit and each other is forced on each slave unit.
Claim 8
Dependent Claim
36 words
Apparatus as claimed in any of claims 1 to 4 incorporated in each of a pair of independently clocked units, wherein, for each unit, one pulse train is derived from the clock of the other unit.
Claim 9
Dependent Claim
29 words
A digital system having a pair of master units as claimed in claim 7, each with one or more slave units as claimed in claim 5 or claim 6.
Claim 10
Dependent Claim
245 words
A digital phase lock loop for phase-aligning a first oscillator signal CLK₁ having a frequency f₁ - one pulse train - and a second oscillator signal CLK₂ having a frequency f₂ nominally equal to f₁ -the other pulse train -, comprising the apparatus of any of claims 1 to 4, wherein the first comparator is a local digital phase comparator for comparing the phase of CLK₂ with the phase of a corrected oscillator signal CLK 1c , and for producing a delay control signal based upon the comparison; the control means comprises digital selection logic connected to the local digital phase comparator for generating delay signals in a delay signal sequence in response to a succession of delay control signals; the delay elements form part of a variable digital delay circuit for receiving CLK₁ and connected to the digital selection logic for producing CLK 1C by adjusting the phase of CLK₁ by delaying CLK₁ an amount of time which changes with the delay signal sequence; and the second comparator is a reset digital phase comparator for comparing the phase of CLK 1C with a CLK reference phase signal produced by the variable digital delay circuit and for producing a reset signal when the phases of CLK 1C and reference phase signal are substantially equal; the reset means being operative on the digital selection logic to generate a delay signal corresponding to a predetermined point in the delay signal sequence in response to the reset signal.
Claim 11
Dependent Claim
85 words
A digital phase lock loop as claimed in claim 9, wherein the digital variable delay means includes: the series of digital delay elements; a plurality of AND elements, each having a first input connected to receive CLK₁ through a respective digital delay element, a second input connected to receive one delay signal in the sequence of delay signals, and an output; and an OR element for receiving the outputs of the AND elements and for generating CLK 1C in response to the AND element outputs.
Claim 12
Dependent Claim
61 words
A digital phase lock loop as claimed in claim 9 or claim 10, wherein the digital selection means includes a multi-stage shift element which moves a delay token signal between adjacent shift stages in response to the control signal, each of the shift stages producing a respective delay signal in the delay signal sequence in response to the delay token signal.
Claim 13
Dependent Claim
118 words
A digital system including a master unit; a reference clock source in the master unit receiving CLK₂ and producing, in response, a phase reference signal REF₂ having a frequency f R =f₂/N, wherein N is a positive integer, greater than one; a slave unit, separate from the master unit; a reference signal source in the slave unit receiving a second clock signal CLK₁ having a frequency f₁ nominally equal to f₂ and producing, in response, a phase reference signal REF₁ having a frequency f R1 =f₁/N; and a digital phase lock loop as claimed in any of claims 9 to 11 in the slave unit, wherein the local digital phase comparator compares the phases of REF₁ and REF₂.
Claim 14
Dependent Claim
103 words
A digital system including an oscillator producing a clock signal CLK₀ having a frequency f₀, a first unit for performing digital functions and including a reference clock source receiving CLK₀ and producing, in response, a phase reference signal REF₀ having a frequency f R =f₀/N, wherein N is a positive integer, greater than one, and a second unit for performing digital functions in synchronism with those of the first unit, a digital phase lock loop as claimed in any of claims 9 to 11 being included in each unit for synchronising the functions of the second unit with those of the first unit.
Claim 15
Dependent Claim
430 words
A complex including two independently-clocked digital systems, adapted to operate in forced synchronism by the provision of: in the first of the systems: a first oscillator producing a first clock signal CLK₁ having a frequency f₁; a first digital phase comparator for comparing the phase of a first clock CLK 1C and a reference clock REF₂, and for producing a delay control signal based upon the comparison; a digital selection means connected to the digital phase comparator for generating delay signals in a delay signal sequence in response to a succession of delay control signals; and a digital variable delay means for receiving CLK₁ and connected to the digital selection means for producing CLK 1C by delaying CLK₁ by an amount of time determined by the delay signal sequence, and a reset phase comparator for comparing the phase of CLK 1C with a CLK₁ reference phase signal produced by the digital variable delay means and for producing a reset signal when the phases of CLK 1C and the reference phase signal are substantially equal; the digital selection means being connected to the reset phase comparator for generating a delay signal at a predetermined point in the delay signal sequence in response to the reset signal; wherein the corrected clock signal CLK 1C is provided by the first system as a system output REF₁; and, in the second of the systems: a second oscillator producing a second clock signal CLK₂ having a frequency f₂ nominally equal to f₁; a digital phase comparator for comparing the phase of a corrected clock signal CLK 2C with the phase of REF₁ and for producing a delay signal based upon the comparison; a digital selection means connected to the digital phase comparator for generating delay signals in a delay signal sequence in response to a succession of delay control signals; and a digital variable delay means for receiving the clock signal CLK₂ and connected to the digital selection means for producing the corrected clock signal CLK 2C by delaying CLK₂ by an amount of time determined by the delay signal sequence; and a reset phase comparator for comparing the phase of CLK 2C with a reference phase of CLK₂ and for producing a reset signal when the phases of CLK 2C and CLK₂ are substantially equal; the digital selection means being connected to the reset phase comparator for generating a delay signal at a predetermined point in the delay signal sequence in response to the reset signal. wherein the corrected clock signal CLK 2C is provided by the second system as a system output REF₂.
Claim 16
Dependent Claim
430 words
A complex including two independently-clocked digital systems, adapted to operate in forced synchronism by the provision of: in the first of the systems: a first oscillator producing a first clock signal CLK₁ having a frequency f₁; a first digital phase comparator for comparing the phase of a first clock CLK 1C and a reference clock REF₂, and for producing a delay control signal based upon the comparison; a digital selection means connected to the digital phase comparator for generating delay signals in a delay signal sequence in response to a succession of delay control signals; and a digital variable delay means for receiving CLK₁ and connected to the digital selection means for producing CLK 1C by delaying CLK₁ by an amount of time determined by the delay signal sequence, and a reset phase comparator for comparing the phase of CLK 1C with a CLK₁ reference phase signal produced by the digital variable delay means and for producing a reset signal when the phases of CLK 1C and the reference phase signal are substantially equal; the digital selection means being connected to the reset phase comparator for generating a delay signal at a predetermined point in the delay signal sequence in response to the reset signal; wherein the corrected clock signal CLK 1C is provided by the first system as a system output REF₁; and, in the second of the systems: a second oscillator producing a second clock signal CLK₂ having a frequency f₂ nominally equal to f₁; a digital phase comparator for comparing the phase of a corrected clock signal CLK 2C with the phase of REF₁ and for producing a delay signal based upon the comparison; a digital selection means connected to the digital phase comparator for generating delay signals in a delay signal sequence in response to a succession of delay control signals; and a digital variable delay means for receiving the clock signal CLK₂ and connected to the digital selection means for producing the corrected clock signal CLK 2C by delaying CLK₂ by an amount of time determined by the delay signal sequence; and a reset phase comparator for comparing the phase of CLK 2C with a reference phase of CLK₂ and for producing a reset signal when the phases of CLK 2C and CLK₂ are substantially equal; the digital selection means being connected to the reset phase comparator for generating a delay signal at a predetermined point in the delay signal sequence in response to the reset signal. wherein the corrected clock signal CLK 2C is provided by the second system as a system output REF₂.
Claim 17
Independent Claim
140 words
A method of phase-aligning a first oscillator signal CLK₁, having a frequency f₁, with a second oscillator signal CLK₂ having a frequency f₂ nominally equal to f₁, comprising the steps of: during a succession of cycles of CLK₂, comparing the phase of CLK₂ with the phase of an oscillating signal CLK 1C having a frequency f 1C =f₁, to produce a sequence of delay control signals; delaying CLK₁ by an amount of time which is successively changed in uniform time units in response to the delay signal sequence; providing CLK 1C based upon the delaying step; comparing the phase of CLK 1C with a predetermined reference phase of CLK₁; and adjusting the amount of time by which CLK₁ is delayed to a predetermined amount corresponding to the reference phase when the phase of CLK 1C equals the phase of CLK₁.
Claim 18
Independent Claim
140 words
A method of phase-aligning a first oscillator signal CLK₁, having a frequency f₁, with a second oscillator signal CLK₂ having a frequency f₂ nominally equal to f₁, comprising the steps of: during a succession of cycles of CLK₂, comparing the phase of CLK₂ with the phase of an oscillating signal CLK 1C having a frequency f 1C =f₁, to produce a sequence of delay control signals; delaying CLK₁ by an amount of time which is successively changed in uniform time units in response to the delay signal sequence; providing CLK 1C based upon the delaying step; comparing the phase of CLK 1C with a predetermined reference phase of CLK₁; and adjusting the amount of time by which CLK₁ is delayed to a predetermined amount corresponding to the reference phase when the phase of CLK 1C equals the phase of CLK₁.
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