Random access memory unit with plural test modes and computer equipped with such units

Abstract

Abstract Random-access memory unit with several test modes, realised as an integrated circuit and not including any specific input/output pins for defining and controlling test mode transition. This unit is equipped with means (1) for detecting whether a predefined sequence of logic signals, which is not contained in a set of normally used sequences, but whose voltages are nevertheless contained within the range of voltages specified for such signals, is delivered to certain inputs (CE, WE, A0), and for placing the unit in test mode when such a sequence has been detected. In order to define the nature of the test to be carried out, terminals (A1-A8) for the address input for the unit are connected to a test-mode decoding circuit (2) in which the data applied to the said input terminals are used as data defining the nature of the test to be carried out. …<IMAGE>…

Inventors

• 👤 Hans Société Civile S.P.I.D. Ontrop
• 👤 Leo Société Civile S.P.I.D. Pfennings
• 👤 Cathal Société Civile S.P.I.D. Phelan
• 👤 Peter Société Civile S.P.I.D. Voss
• 👤 Tom Société Civile S.P.I.D. Davies
• 👤 Cormac Société Civile S.P.I.D. O'Connell
• 👤 Betty Société Civile S.P.I.D. Prince
• 👤 Roelof Société Civile S.P.I.D. Salters

Bibliographic Details