EP0296707A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Incorporation of dielectric layers in a semiconductor
Assignee: HP Inc
•
Filing: 1988-05-11
•
Granted: —
•
Expires: 2008-05-11
Abstract
Abstract A system for integrating a composite dielectric layer in an integrated circuit to facilitate fabrication of a high density multi-level interconnect with external contacts. The composite dielectric layer comprises of a polymer layer (20) which normally comprises a polyimide that is deposited using conventional spin-deposit techniques to form a planarized surface (22) for deposition of an inorganic layer (24), typically comprising silicon dioxide, or silicon nitride. The inorganic layer (24) is etched using standard photoresist techniques to form an inorganic mask (30) for etching the polymer layer (20). A previously deposited inorganic layer functions as an etch stop to allow long over etches to achieve full external contacts which, in turn, allows high density interconnect systems on multiple levels.
Inventors
- 👤 Daniel Dean Kessler
- 👤 Christopher C. Beatty
- 👤 Robert W. Wu
- 👤 Mark D. Crook
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 07:53
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/286; H10P50/287
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
204 words
A process for forming composite dielectric layers in an integrated circuit to facilitate high density multi-level interconnects with external contacts through the use high strength dielectric layers to support high stress metal layers characterized by the steps of: forming a polymer layer (20) on a first inorganic layer of said semiconductor that is substantially uniformly distributed to provide a substantially planarized surface (22); depositing a second inorganic layer (24) in said integrated circuit over said polymer layer (20); forming a mask (28) on said inorganic layer (24): etching said second inorganic layer (24) using said mask (28) as a masking pattern to form an inorganic mask (30) and provide a protective layer for etching of any subsequently deposited polymer layers; etching said polymer layer (20) using said inorganic mask (30) as a masking pattern to essentially remove all polymer (20) unmasked by said inorganic mask (30) between said inorganic mask (30) and said first inorganic layer (14) such that said first inorganic layer (14) functions as a protective layer whenever said etching of said polymer layer continues after all of said unmasked polymer has been removed to fully expose external contact surfaces (36,38) of conductors to be connected to subsequently deposited metal layers (40,42).
Claim 2
Dependent Claim
204 words
A process for forming composite dielectric layers in an integrated circuit to facilitate high density multi-level interconnects with external contacts through the use high strength dielectric layers to support high stress metal layers characterized by the steps of: forming a polymer layer (20) on a first inorganic layer of said semiconductor that is substantially uniformly distributed to provide a substantially planarized surface (22); depositing a second inorganic layer (24) in said integrated circuit over said polymer layer (20); forming a mask (28) on said inorganic layer (24): etching said second inorganic layer (24) using said mask (28) as a masking pattern to form an inorganic mask (30) and provide a protective layer for etching of any subsequently deposited polymer layers; etching said polymer layer (20) using said inorganic mask (30) as a masking pattern to essentially remove all polymer (20) unmasked by said inorganic mask (30) between said inorganic mask (30) and said first inorganic layer (14) such that said first inorganic layer (14) functions as a protective layer whenever said etching of said polymer layer continues after all of said unmasked polymer has been removed to fully expose external contact surfaces (36,38) of conductors to be connected to subsequently deposited metal layers (40,42).
Claim 3
Dependent Claim
34 words
A process according to claim 1 wherein said step of depositing said first inorganic layer (14), comprises depositing and etching a second inorganic layer of composite dielectric layers previously formed on said integrated circuit.
Claim 4
Dependent Claim
57 words
A process according to claim 1 or 2 wherein said step of forming said polymer layer (20) comprises the steps of: depositing a polymer (20) suspended in a solvent on said inorganic layer (14); uniformly distributing said polymer (20) suspended in said solvent by spinning said integrated circuit; thermally curing said polymer (20) to remove said solvent.
Claim 5
Dependent Claim
30 words
A process according to any of claims 1 to 3 wherein said step of depositing said second inorganic layer (24) comprises applying silicon dioxide using plasma enhanced chemical vapor deposition.
Claim 6
Dependent Claim
28 words
A process according to any of claims 1 to 3 wherein said step of depositing said second inorganic layer (24) comprises applying silicon dioxide using atmospheric pressure deposition.
Claim 7
Dependent Claim
30 words
A process according to any of claims 1 to 3 wherein said step of depositing said second inorganic layer (24) comprises applying silicon nitride using plasma enhanced chemical vapor deposition.
Claim 8
Dependent Claim
78 words
A process according to any of claims 1 to 6 wherein said step of forming a mask (28) on said second inorganic layer (24) comprises: depositing a photoresist layer on said second inorganic layer that is highly planarized so that small features can be transferred to said polymer layer; exposing said photoresist layer using photolithographic techniques with a predetermined masking pattern; etching said photoresist layer to produce a photoresist mask (28) essentially corresponding to said predetermined masking pattern.
Claim 9
Dependent Claim
35 words
A process according to any of claims 1 to 7 wherein said step of etching said second inorganic layer (24) comprises dry etching said second inorganic layer with carbon tetrafloride in a reactive ion etcher.
Claim 10
Dependent Claim
37 words
A process according to any of claims 1 to 8 wherein said step of etching said polymer layer (20) comprises dry etching said polymer layer (20) with oxygen and noble gas ions in a reactive ion etcher.
Claim 11
Dependent Claim
93 words
A composite dielectric layer in a semiconductor characterized by: polymer layer means (20) deposited over a preselected surface of said semiconductor for forming a substantially planarized surface (22) suitable for submicron etching of features to be formed in said composite dielectric layer; inorganic layer means (24) deposited over said polymer layer means for forming a mask (30) during the etching of said polymer layer (20) and for providing a protective layer during etching of subsequently deposited polymer layers and provide a composite structure that is sufficiently strong to support high stress metal layers.
Claim 12
Dependent Claim
93 words
A composite dielectric layer in a semiconductor characterized by: polymer layer means (20) deposited over a preselected surface of said semiconductor for forming a substantially planarized surface (22) suitable for submicron etching of features to be formed in said composite dielectric layer; inorganic layer means (24) deposited over said polymer layer means for forming a mask (30) during the etching of said polymer layer (20) and for providing a protective layer during etching of subsequently deposited polymer layers and provide a composite structure that is sufficiently strong to support high stress metal layers.
Claim 13
Dependent Claim
17 words
A multi-level dielectric layer according to claim 10 wherein said polymer layer means (20) is a polyimide.
Claim 14
Dependent Claim
19 words
A multi-level dielectric layer according to claim 10 or 11 wherein said inorganic layer means (24) is silicon dioxide.
Claim 15
Dependent Claim
19 words
A multi-level dielectric layer according to claim 10 or 11 wherein said inorganic layer means (24) is silicon nitride.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.