EP0103879A1
Expired / Lapsed
EP
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Method of manufacturing a monolithic integrated circuit
Assignee: Siemens AG
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Filing: 1983-09-19
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Granted: —
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Expires: 2003-09-19
Abstract
Abstract In manufacturing a monolithic integrated semiconductor circuit having at least two conductor track levels arranged above one another, the structured metallisation last applied is always first covered with a polyimide layer and the latter with a silicon nitride layer produced by plasma discharge. The latter is used as a substrate for the fresh conductor track level to be applied. In this way, open circuits at the crossing points of conductor tracks, in particular of aluminium, are avoided. In addition, the adhesive capacity is improved compared with conductor tracks applied directly to a polyimide base. <IMAGE>
Inventors
- 👤 Harald Dipl.-Ing. Eggers
- 👤 Andreas Dipl.-Phys. Glasl
- 👤 Manfred Dipl.-Ing. Kerschbaum
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 05:07
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/694; H10P14/6943; H10P14/69433; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/074; H10W20/081; H10W20/40; H10W20/45; H10W20/48
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References Cited (Backward Citations)
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