EP0283907A1
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Circuit arrangement and method for testing memory cells
Assignee: Siemens AG
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Filing: 1988-03-15
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Granted: —
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Expires: 2008-03-15
Abstract
Abstract For testing memory cells (SZ), a pair of external bit lines (XB, XB) are precharged to mutually complementary logic levels. All the memory cells (SZ) of a word line (WL) are always read out parallel to one another. If "in order", the pair of external bit lines (XB, XB) retains its precharged level, if there is an error the level of that external bit line which is precharged to logical 1 drops. This is detected and evaluated by a discriminator circuit (DISC). <IMAGE>
Inventors
- 👤 Hans-Dieter Dipl.-Ing. Oberle
- 👤 Kurt Dr. Prof. Hoffmann
- 👤 Oskar Dr. Rer. Nat. Kowarik
- 👤 Rainer Dipl.-Phys. Kraus
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 22:55
CPC Classifications
G; G11; G11C; G11C29/00; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G11C29/36; G11C29/38; H03K19/08; H03K19/094; H03K19/096; H03K19/0963
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References Cited (Backward Citations)
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