Write request buffering apparatus

Claim 2

Apparatus for buffering write requests to an output device, each write request having associated therewith data and an address, the apparatus (10) comprising: a first buffer rank (70a,80a); a second buffer rank (70b,80b) different from the first buffer rank (70a,80a); means (72a,82a) for writing a first one of the write requests into the first buffer rank (70a,80a); means (74,84) for emptying write requests from the buffer ranks (70a,80a,70b,80b); means (50a,62a,72a,82a) for writing a second one of the write requests into the first buffer rank (70a,80a) if the first buffer rank is empty; means (72b,82b,94) for writing the second one of the write requests into the second buffer rank (70b,80b) if the first buffer rank is non-empty and the address associated with the first one of the write requests does not match the address associated with the second one of the write requests; and means (90,92,94,104) for gathering the second one of the write requests with the first one of the write requests in the first buffer rank (70a,80a) if the address associated with the second one of the write requests matches the address associated with the first one of the write requests and the first buffer rank (70a,80a) is non-empty.

Claim 3

Apparatus according to claim 1, wherein the means (90,92,94,104) for gathering the second one of the write requests with the first one of the write requests in the first buffer rank (70a,80a) comprises means for writing into the first buffer rank (70a,80a) only those bits of the data associated with the second write request which are intended to be written to the output device.

Claim 4

Apparatus for buffering write requests to an output device, each write request having associated therewith a data word, a word address, and a valid signal for pointing to those bits of the data word which are to be written to the output device, the apparatus (10) comprising: a plurality of buffer ranks, each buffer rank comprising a data register (70) for holding a data word, an address register (80) for holding the word address to which data from the data word is to be written, and a valid register (50) for pointing to the bits of the data register (70) which are to be written, the buffer rank being considered empty if the valid register (50) points to none of the bits of the data register (70) and non-empty if the valid register (50) points to at least one of the bits of the data register (70); means (82) for writing the word address of a first incoming write request into the address register (80) of a first input one of the buffer ranks; means (72) for writing into the data register (70) of the first input one of the buffer ranks only those bits of the data word of the first incoming write request which are pointed to by the valid signal of the first incoming write request; and means (52) for altering the contents of the valid register (50) of the first input one of the buffer ranks so as to point to the bits pointed to by the valid signal of the first incoming write request as well as the bits pointed to by the valid register (50) immediately before activation of the altering means (52).

Claim 5

Apparatus for buffering write requests to an output device, each write request having associated therewith a data word, a word address, and a valid signal for pointing to those bits of the data word which are to be written to the output device, the apparatus (10) comprising: a plurality of buffer ranks, each buffer rank comprising a data register (70) for holding a data word, an address register (80) for holding the word address to which data from the data word is to be written, and a valid register (50) for pointing to the bits of the data register (70) which are to be written, the buffer rank being considered empty if the valid register (50) points to none of the bits of the data register (70) and non-empty if the valid register (50) points to at least one of the bits of the data register (70); means (82) for writing the word address of a first incoming write request into the address register (80) of a first input one of the buffer ranks; means (72) for writing into the data register (70) of the first input one of the buffer ranks only those bits of the data word of the first incoming write request which are pointed to by the valid signal of the first incoming write request; and means (52) for altering the contents of the valid register (50) of the first input one of the buffer ranks so as to point to the bits pointed to by the valid signal of the first incoming write request as well as the bits pointed to by the valid register (50) immediately before activation of the altering means (52).

Claim 6

Apparatus according to claim 3, comprising: means (58,74,84) for emptying an output one of the buffer ranks and altering the valid register (50) of the output one of the buffer ranks so as to point to none of the bits of the data register (70) of the output one of the buffer ranks; wherein the first input one of the buffer ranks is chosen to be a non-empty buffer rank the address register (80) of which holds a word address which matches the word address of the first incoming write request, or, if the address register (80) of none of the non-empty buffer ranks holds a word address which matches the word address of the first incoming write request, an empty buffer rank.

Claim 7

Apparatus according to claim 3, comprising: means (58,74,84) for emptying an output one of the buffer ranks and altering the valid register (50) of the output one of the buffer ranks so as to point to none of the bits of the data register (70) of the output one of the buffer ranks; wherein the first input one of the buffer ranks is chosen to be a non-empty buffer rank different from the output one of the buffer ranks, the address register (80) of which holds a word address which matches the word address of the first incoming write request, or, if the address register (80) of none of the non-empty buffer ranks different from the output one of the buffer ranks holds a word address which matches the word address of the first incoming write request, an empty buffer rank.

Claim 8

Apparatus according to claim 3, comprising: means (58,74,84) for emptying an output one of the buffer ranks and altering the valid register (50) of the output one of the buffer ranks so as to point to none of the bits of the data register (70) of the output one of the buffer ranks; means (82) for writing the word address of a second incoming write request into the address register (80) of a second input one of the buffer ranks, the second incoming write request following the first incoming write request without any intervening write requests; means (72) for writing into the data register (70) of the second input one of the buffer ranks only those bits of the data word of the second incoming write request which are pointed to by the valid signal of the second incoming write request; and means (52) for altering the contents of the valid register (50) of the second input one of the buffer ranks so as to point to the bits pointed to by the valid signal of the second incoming write request as well as the bits pointed to by the valid register of the second input one of the buffer ranks immediately before activation of the altering means (52); wherein the second input one of the buffer ranks is chosen to be the first input one of the buffer ranks if the word address of the second incoming write request matches the word address of the first incoming write request and the first input one of the buffer ranks is non-empty, or, if the word address of the second incoming write request does not match the word address of the first incoming write request, or it the first input one of the buffer ranks is empty, an empty buffer rank.

Claim 9

Apparatus for buffering write request to an output device, each write request comprising a data word and a destination address, the apparatus (10) comprising; a buffer (70,80) capable of storing at least two write requests; means (74,84) for removing write requests from the buffer (70,80); means (90,92,94,104) for gathering an incoming write request with a previous write request in the buffer (70,80), which previous write request has not been removed and the destination address of which previous write request matches the destination address of the incoming write request; and means (72,82) for storing the incoming write request in the buffer (70,80) if the destination address of the incoming write request does not match the destination address of any write request in the buffer, which write request has not be removed.

Claim 10

Apparatus for buffering write request to an output device, each write request comprising a data word and a destination address, the apparatus (10) comprising; a buffer (70,80) capable of storing at least two write requests; means (74,84) for removing write requests from the buffer (70,80); means (90,92,94,104) for gathering an incoming write request with a previous write request in the buffer (70,80), which previous write request has not been removed and the destination address of which previous write request matches the destination address of the incoming write request; and means (72,82) for storing the incoming write request in the buffer (70,80) if the destination address of the incoming write request does not match the destination address of any write request in the buffer, which write request has not be removed.

Claim 11

Apparatus according to claim 7, wherein each write request comprises a valid signal indicating which bits of the destination address of such write request are to receive data from the data word of such write request, and wherein the means (90,92,94,104) for gathering an incoming write request with a previous write request in the buffer (70,80), which write request has not been removed, comprises means for generating a resulting write request in which: (a) those bits of the destination address of the resulting write request which, according to the valid signal of the incoming write request, are to receive data from the data word of the incoming write request, are indicated by the resulting write request to receive data from the data word of the incoming write request; and (b) those bits of the destination address of the resulting write request which, according to the valid signal of the previous write request, are to receive data from the data word of the previous write request, and which, according to the valid signal of the incoming write request, are not also to receive data from the data word of the incoming write request, are indicated by the resulting write request to receive data from the data word of the previous write request.

Claim 12

Apparatus according to claim 8, wherein the gathering means comprises means for overwriting the previous write request with the resulting write request.

Claim 13

Apparatus for buffering write requests to an output device, each write request comprising a data word and a destination address, the apparatus (10) comprising: a buffer (70,80) capable of storing at least two write requests; means (74,84) for removing write requests from the buffer (70,80), including means (50) for pointing to the next write request to be removed from the buffer (70,80); means (90,92,94,104) for gathering an incoming write request with a previous write request in the buffer (70,80), which previous write request has not been removed, is not pointed to by the pointing means (50), and the destination address of which previous write request matches the destination address of the incoming write request; and means (72,82) for storing the incoming write request in the buffer (70,80) if the destination address of the incoming write request does not match the destination address of any write request in the buffer (70,80), which write request has not been removed.

Claim 14

Apparatus for buffering write requests to an output device, each write request comprising a data word and a destination address, the apparatus (10) comprising: a buffer (70,80) capable of storing at least two write requests; means (74,84) for removing write requests from the buffer (70,80), including means (50) for pointing to the next write request to be removed from the buffer (70,80); means (90,92,94,104) for gathering an incoming write request with a previous write request in the buffer (70,80), which previous write request has not been removed, is not pointed to by the pointing means (50), and the destination address of which previous write request matches the destination address of the incoming write request; and means (72,82) for storing the incoming write request in the buffer (70,80) if the destination address of the incoming write request does not match the destination address of any write request in the buffer (70,80), which write request has not been removed.

Claim 15

Apparatus for buffering write requests to an output device, each write request comprising a data word and a destination address, the apparatus (10) comprising: a buffer (70,80) capable of storing at least two write requests; means (74,84) for removing write requests from the buffer (70,80); means (90,92,94,104) for gathering an incoming write request with an immediately preceding write request if such immediately preceding write request has not been removed and the destination address of such immediately preceding write request matches the destination address of the incoming write request; and means (72,82) for storing the incoming write request in the buffer (70,80) if the destination address of the incoming write request does not match the destination address of the immediately preceding write request or if such immediately preceding write request has been removed.

Claim 16

Apparatus for buffering write requests to an output device, each write request comprising a data word and a destination address, the apparatus (10) comprising: a buffer (70,80) capable of storing at least two write requests; means (74,84) for removing write requests from the buffer (70,80); means (90,92,94,104) for gathering an incoming write request with an immediately preceding write request if such immediately preceding write request has not been removed and the destination address of such immediately preceding write request matches the destination address of the incoming write request; and means (72,82) for storing the incoming write request in the buffer (70,80) if the destination address of the incoming write request does not match the destination address of the immediately preceding write request or if such immediately preceding write request has been removed.