Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
197 words
A data reading circuit for a semiconductor memory device comprising: a first input terminal and a second input terminal for receiving complementary signals (DB, DB); and, a first (12) and a second (11) current mirror type sense amplifier, each of the current mirror type sense amplifiers (12, 11) including: a reference node (Nl, N2); an output terminal; a first transistor (Q3, Q8) connected with the reference node (Nl, N2); and a second transistor (Q4, Q9) connected with the output terminal, the gate of the first transistor (Q3) of the first sense amplifier (12) and the gate of the second transistor (Q9) of the second sense amplifier (11) being connected to the first input terminal, and the gate of the second transistor (Q4) of the first sense amplifier (12) and the gate of the first transistor (Q8) of the second sense amplifier (11) being connected to the second input terminal; characterised in that the circuit also includes a first short-circuiting transistor (72) connected between the reference nodes (NI, N2) of both the first (12) and second (11) sense amplifiers, the first short-ciruiting transistor (72) temporarily conducting upon receipt of a clock signal (φ 2 ) at its gate.
Claim 2
Dependent Claim
197 words
A data reading circuit for a semiconductor memory device comprising: a first input terminal and a second input terminal for receiving complementary signals (DB, DB); and, a first (12) and a second (11) current mirror type sense amplifier, each of the current mirror type sense amplifiers (12, 11) including: a reference node (Nl, N2); an output terminal; a first transistor (Q3, Q8) connected with the reference node (Nl, N2); and a second transistor (Q4, Q9) connected with the output terminal, the gate of the first transistor (Q3) of the first sense amplifier (12) and the gate of the second transistor (Q9) of the second sense amplifier (11) being connected to the first input terminal, and the gate of the second transistor (Q4) of the first sense amplifier (12) and the gate of the first transistor (Q8) of the second sense amplifier (11) being connected to the second input terminal; characterised in that the circuit also includes a first short-circuiting transistor (72) connected between the reference nodes (NI, N2) of both the first (12) and second (11) sense amplifiers, the first short-ciruiting transistor (72) temporarily conducting upon receipt of a clock signal (φ 2 ) at its gate.
Claim 3
Dependent Claim
49 words
A data reading circuit according to claim 1, which further comprises a second short-circuiting transistor (71), connected between the output terminals of the first (12) and second (11) sense amplifiers, the second short-circuiting transistor (71) temporarily conducting upon receipt of the clock signal ($ 2 ) at its gate.
Claim 4
Dependent Claim
91 words
A data reading circuit according to claim 1 or 2, wherein the first sense amplifier (12) is composed of five transistors (Q3 to Q7), the second sense amplifier (11) is composed of five transistors (Q8 to Q12), and transistors Q3, Q4, Q7, Q8, Q9, Q12 and the first short circuiting transistor (71) are N-channel MOS transistors, while transistors Q5, Q6, Q10 and Q11 are P-channel MOS transistors and the first (12) and second (11) sense amplifiers are both current mirror type sense amplifiers which are formed by a respective CMOS circuit.
Claim 5
Dependent Claim
27 words
A data reading circuit according to any one of the preceding claims, which further comprises a third short-circuiting transistor connected between the first and second input terminals.