High density, high voltage FET

Claim 2

High density, high voltage lateral FET structure, comprising: a source region of one conductivity type semiconductor material; a channel region of opposite conductivity type semiconductor material forming a junction with said source region; a drift region of said one conductivity type semiconductor material forming another junction with said channel region; first circuit connection means communicating with said source region; second circuit connection means communicating with said drift region; an insulative region in said drift region between said channel region and said second circuit connection means; gate means disposed proximate said channel region and adapted for application of an electrical potential for producing an electric field of sufficient intensity - to invert the conductivity type in said channel region; whereby upon application of voltage across said first and second circuit connection means, electric current can flow therebetween under control of said electrical potential of said gate means, and such that in the absence of said electrical gate potential, said insulative region prevents induced conductive channel inversion through said drift region, to enhance OFF state voltage blocking capability.

Claim 3

The invention according to Claim 1 wherein each of said regions is disposed along a top major surface of a semiconductor substrate, and wherein said insulative region extends downwardly from said top major surface to divert conductive current paths therearound between said channel region and said second circuit connection means, whereby to lengthen the drift region conductive path, so as to sustain higher blocking voltage, without increasing the lateral dimension along said top major surface.

Claim 4

The invention according to Claim 2 wherein said drift region extends around the bottom of said insulative region and then upwardly along each side of said insulative region to said top major surface, said channel region and said insulative region being laterally spaced by the left upward extension of said drift region, and said second circuit connection means and said insulative region being spaced by the right upward extension of said drift region.

Claim 5

The invention according to Claim 3 wherein said source region and said left upward extension of said drift region are laterally spaced by said channel region.

Claim 6

The invention according to Claim 4 wherein said channel region is part of a tub region of said opposite conductivity type extending laterally at least partially around said source region.

Claim 7

The invention according to Claim 5 wherein said first circuit connection means is connected to said source region and said tub region to ohmically short said source region and said channel region.

Claim 8

The invention according to Claim 6 wherein said gate means comprises a gate electrode extending laterally along said top major surface and spaced thereabove by a layer of insulation, said gate electrode extending across said channel region and at least partially across said left upward extension of said drift region between said channel region and said insulative region.

Claim 9

The invention according to Claim 2 wherein said insulative region comprises porous silicon filled with oxide to substantially reduce the conductivity therethrough and effectively divert conduction paths therearound.

Claim 10

A bidirectional FET, comprising: a first source region of one conductivity type semiconductor material; a first channel region of opposite conductivity type semiconductor material forming a junction with said first source region; a drift region of said one conductivity type semiconductor material forming another junction with said first channel region; a second channel region of said opposite conductivity type semiconductor material forming a junction with said drift region; a second source region of said one conductivity type semiconductor material forming a junction with said second channel region; an insulative region formed in said drift region between said first and second channel regions; gate means disposed proximate said first and second channel regions and adapted for application of an electrical potential for producing electric fields of sufficient intensity to invert the conductivity type in said first and second channel regions; whereby upon application of voltage of either polarity to said first and second source regions, electric current can flow in a repective corresponding direction between them, under control of said electrical potential of said gate means, the conductive current path through said drift region being diverted around said insulative region to increase the length of said drift region current path.

Claim 11

A bidirectional FET, comprising: a first source region of one conductivity type semiconductor material; a first channel region of opposite conductivity type semiconductor material forming a junction with said first source region; a drift region of said one conductivity type semiconductor material forming another junction with said first channel region; a second channel region of said opposite conductivity type semiconductor material forming a junction with said drift region; a second source region of said one conductivity type semiconductor material forming a junction with said second channel region; an insulative region formed in said drift region between said first and second channel regions; gate means disposed proximate said first and second channel regions and adapted for application of an electrical potential for producing electric fields of sufficient intensity to invert the conductivity type in said first and second channel regions; whereby upon application of voltage of either polarity to said first and second source regions, electric current can flow in a repective corresponding direction between them, under control of said electrical potential of said gate means, the conductive current path through said drift region being diverted around said insulative region to increase the length of said drift region current path.

Claim 12

10 . The invention according to Claim 9 wherein said channel regions are laterally spaced by said drift region, and said insulative region extends downwardly between said channel regions from a top major surface of said FET, said drift region having right and left upward extensions extending upwardly to said top major surface between said insulative region and said channel regions on opposite sides thereof.

Claim 13

The invention according to Claim 1 0 wherein said source regions are laterally spaced along said top major surface, and wherein said channel regions, said left and right upward extension drift region portions, and said insulative region are disposed between said source regions.

Claim 14

The invention according to Claim 11 comprising a pair of main electrodes each connected to a respective said source region, and wherein said gate means comprises gate electrode means extending laterally along said top major surface and spaced thereabove by a layer of insulation, said gate electrode means including at least portions extending across said first channel region and across said second channel region.

Claim 15

The invention according to Claim 1 2 wherein said FET has an OFF state in the absence of said electric gate potential, with the junction between said drift region and one of said channel regions blocking current flow toward one of said main electrodes, and with the junction between said drift region and the other of said channel regions blocking current flow toward the other of said main electrodes.

Claim 16

The invention according to Claim 13 wherein the drift region current path between said main electrodes is diverted downwardly around the bottom of said insulative region so as to increase the drift region current path length so as to afford higher OFF state voltage blocking capability, without increasing the lateral dimension between said channel regions, whereby to afford a high density, high voltage FET structure.

Claim 17

The invention according to Claim 1 4 wherein carrier attraction in said drift region toward said top major surface in said OFF state is diminished by the increased separation provided by said insulative region whereby to decrease the carrier concentration along said top major surface adjacent said gate electrode means and prevent undesired inducement of conduction channels through said drift region in said OFF state.

Claim 18

The invention according to Claim 15 wherein said gate electrode means comprises a split gate structure including a first gate electrode extending across said first channel region and at least partially across said left upward extension drift region portion, and including a second gate electrode extending across said second channel region and then at least partially across said right upward extension drift region portion.

Claim 19

The invention according to Claim 16 wherein each of said gate electrodes is referencable to a respective one of said main electrodes in said OFF state of said FET, while still maintaining said high voltage blocking capability.

Claim 20

The invention according to Claim 11 wherein said channel regions are part of respective tub regions of said opposite conductivity type extending laterally at least partially around respective said source regions, and comprising a pair of main electrodes each connected to a respective said source region and its respective said tub region to ohmically short each respective said source and channel region.

Claim 21

1 9. The invention according to Claim 14 wherein said insulative region comprises porous silicon filled with oxide to substantially diminish the conductivity therethrough.

Claim 22

The invention according to Claim 14 wherein said insulative region comprises an anisotropically etched groove filled with oxide.

Claim 23

A bidirectional laterally integrated power switching plural FET structure, comprising: a substrate of semiconductor material of one conductivity type having a top major surface; a first tub region of the other conductivity type in said substrate along said top major surface; first and second source region portions of said one conductivity type in said first tub region laterally spaced along said top major surface; a second tub region of said other conductivity type in said substrate laterally spaced from said first tub region along said top major surface; third and fourth source region portions of said one conductivity type in said second tub region laterally spaced along said top major surface; third, fourth, and so on, tub regions in said substrate, having fifth and sixth, seventh and eighth, and so on, source region portions; a first insulative region in said substrate extending downwardly from said top major surface to a predetermined depth and laterally spaced between said first and second tub regions; a second insulative region in said substrate extending downwardly from said top major surface to a predetermined depth and laterally spaced between said second and third tub regions; third, fourth, and so on, insulative regions in said substrate between said second and third, and so on tub regions; first gate electrode means insulatingly spaced above said top major surface and including at least a portion extending across the section of said first tub region between said second source region portion and said substrate, and at least a portion extending across the section of said second tub region between said substrate and said third source region portion; second gate electrode means insulatingly spaced above said top major surface and including at least a portion extending across the section of said second tub region between said fourth source region portion and said substrate, and at least a portion extending across the section of said third tub region between said substrate and said fifth region portion; third, fourth, and so on, gate electrode means; a first main electrode ohmically connected to said first and second source region portions and the section of said first tub region therebetween; a second main electrode ohmically connected to said third and fourth source region portions and the section of said second tub region therebetween; third, fourth, and so on, main electrodes; said section of said first tub region between said second source region portion and said substrate comprising a first channel region along said top major surface, and said section of said second tub region between said substrate and said third source region portion comprising a second channel region along said top major surface, such that given gate potential on said first gate electrode means attracts given polarity carriers to invert said first and second channel regions to said one conductivity type such that current may flow in either direction between said first and second main electrodes; said section of said second tub region between, said fourth source region portion and said substrate comprising a third channel region, and said section of said third tub region between said substrate and said fifth source region portion comprising a fourth channel region such that given gate potential on said second gate electrode means attracts said given polarity carriers and inverts said third and fourth channel regions to said one conductivity type such that current may flow in either direction between said second and third main electrodes, and so on; said FET structure having an OFF state in the absence of said given gate potential, said insulative regions providing increased drift region path lengths therearound to increase the OFF state voltage blocking capability without increasing the lateral dimension between said channel regions.

Claim 24

A bidirectional laterally integrated power switching plural FET structure, comprising: a substrate of semiconductor material of one conductivity type having a top major surface; a first tub region of the other conductivity type in said substrate along said top major surface; first and second source region portions of said one conductivity type in said first tub region laterally spaced along said top major surface; a second tub region of said other conductivity type in said substrate laterally spaced from said first tub region along said top major surface; third and fourth source region portions of said one conductivity type in said second tub region laterally spaced along said top major surface; third, fourth, and so on, tub regions in said substrate, having fifth and sixth, seventh and eighth, and so on, source region portions; a first insulative region in said substrate extending downwardly from said top major surface to a predetermined depth and laterally spaced between said first and second tub regions; a second insulative region in said substrate extending downwardly from said top major surface to a predetermined depth and laterally spaced between said second and third tub regions; third, fourth, and so on, insulative regions in said substrate between said second and third, and so on tub regions; first gate electrode means insulatingly spaced above said top major surface and including at least a portion extending across the section of said first tub region between said second source region portion and said substrate, and at least a portion extending across the section of said second tub region between said substrate and said third source region portion; second gate electrode means insulatingly spaced above said top major surface and including at least a portion extending across the section of said second tub region between said fourth source region portion and said substrate, and at least a portion extending across the section of said third tub region between said substrate and said fifth region portion; third, fourth, and so on, gate electrode means; a first main electrode ohmically connected to said first and second source region portions and the section of said first tub region therebetween; a second main electrode ohmically connected to said third and fourth source region portions and the section of said second tub region therebetween; third, fourth, and so on, main electrodes; said section of said first tub region between said second source region portion and said substrate comprising a first channel region along said top major surface, and said section of said second tub region between said substrate and said third source region portion comprising a second channel region along said top major surface, such that given gate potential on said first gate electrode means attracts given polarity carriers to invert said first and second channel regions to said one conductivity type such that current may flow in either direction between said first and second main electrodes; said section of said second tub region between, said fourth source region portion and said substrate comprising a third channel region, and said section of said third tub region between said substrate and said fifth source region portion comprising a fourth channel region such that given gate potential on said second gate electrode means attracts said given polarity carriers and inverts said third and fourth channel regions to said one conductivity type such that current may flow in either direction between said second and third main electrodes, and so on; said FET structure having an OFF state in the absence of said given gate potential, said insulative regions providing increased drift region path lengths therearound to increase the OFF state voltage blocking capability without increasing the lateral dimension between said channel regions.

Claim 25

The invention according to Claim 21 wherein said gate electrode means are referencable to at least one of said main electrodes in said OFF state, said insulative regions providing increased separation of substrate regions therebeneath from said top major surface so as to diminish the attrative force exerted by said gate electrode means on given polarity carriers in said substrate during said OFF state, whereby to prevent undesired inducement of conductivity inversion conduction channels through said substrate, and afford enhanced OFF state voltage blocking capability.

Claim 26

The invention according to Claim 22 comprising means ohmically interconnecting said gate electrode means, means ohmically interconnecting said first, third, fifth, and so on main electrodes, and means ohmically interconnecting said second, fourth, and so on, main electrodes.

Claim 27

An integrated plural lateral FET structure for bidirectional power switching, comprising: a semiconductor chip comprising a substrate of one conductivity type; a plurality of laterally spaced cells forming a matrix array on said substrate along a top major surface thereof; each said cell having a right portion forming a lateral FET in combination with the left portion of the next adjacent cell to the right; each cell having a left portion forming a lateral FET in combination with the right portion of the next adjacent cell to the left; each cell comprising: a tub region of opposite conductivity type in said substrate and extending laterally and then upwardly to said top major surface to form right and left boundaries defining right and left junctions with said substrate; source region means of said one conductivity type in said tub region and having left and right portions extending laterally and then upwardly to said top major surface to define right and left junctions with said right and left upward extensions of said tub region; said right and left upward extensions of said tub region forming right and left FET channels immediately below said top major surface; said right and left source region portions also extending laterally towards each other and then upwardly to said top major surface such that an intermediate portion of said tub region extends upwardly to said top major surface between said right and left source region portions; a plurality of laterally spaced insulative regions forming a matrix array on said substrate along said top major surface and extending downwardly into said substrate to a predetermined depth, each said insulative region spaced laterally between a right said cell and a left said cell; first main electrode means ohmically interconnecting said upwardly extending intermediate tub region portion at said top major surface with the intermediate tub region portion of alternate cells; second main electrode means ohmically interconnecting said upwardly extending intermediate tub region portions of the remaining alternate cells; gate electrode means insulated above said top major surface of said substrate in a waffle like matrix pattern with each respective gate electrode section including at least a portion overlying and extending across said right FET channel of a left cell, and at least a portion extending across said left FET channel of a right cell; said substrate having a left portion extending upwardly to said top major surface between said insulative region and a left said cell, and having a right portion extending upwardly to said top major surface between said insulative region and a right said cell, said insulative region and said right and left upward substrate extensions likewise forming a waffle like pattern separating the rows and columns of said cells in said matrix array.

Claim 28

An integrated plural lateral FET structure for bidirectional power switching, comprising: a semiconductor chip comprising a substrate of one conductivity type; a plurality of laterally spaced cells forming a matrix array on said substrate along a top major surface thereof; each said cell having a right portion forming a lateral FET in combination with the left portion of the next adjacent cell to the right; each cell having a left portion forming a lateral FET in combination with the right portion of the next adjacent cell to the left; each cell comprising: a tub region of opposite conductivity type in said substrate and extending laterally and then upwardly to said top major surface to form right and left boundaries defining right and left junctions with said substrate; source region means of said one conductivity type in said tub region and having left and right portions extending laterally and then upwardly to said top major surface to define right and left junctions with said right and left upward extensions of said tub region; said right and left upward extensions of said tub region forming right and left FET channels immediately below said top major surface; said right and left source region portions also extending laterally towards each other and then upwardly to said top major surface such that an intermediate portion of said tub region extends upwardly to said top major surface between said right and left source region portions; a plurality of laterally spaced insulative regions forming a matrix array on said substrate along said top major surface and extending downwardly into said substrate to a predetermined depth, each said insulative region spaced laterally between a right said cell and a left said cell; first main electrode means ohmically interconnecting said upwardly extending intermediate tub region portion at said top major surface with the intermediate tub region portion of alternate cells; second main electrode means ohmically interconnecting said upwardly extending intermediate tub region portions of the remaining alternate cells; gate electrode means insulated above said top major surface of said substrate in a waffle like matrix pattern with each respective gate electrode section including at least a portion overlying and extending across said right FET channel of a left cell, and at least a portion extending across said left FET channel of a right cell; said substrate having a left portion extending upwardly to said top major surface between said insulative region and a left said cell, and having a right portion extending upwardly to said top major surface between said insulative region and a right said cell, said insulative region and said right and left upward substrate extensions likewise forming a waffle like pattern separating the rows and columns of said cells in said matrix array.

Claim 29

The invention according to Claim 24 wherein said upwardly extending intermediate tub region portion is offset to the right or left of center in said cells such that said main .electrode connection point is likewise offset to the right or left in each cell; in a first row of cells, each cell having said main electrode connection point to the left of center to thus have a left hand orientation; in the second row of cells, each cell having said main electrode connection point to the right of center to thus have a right hand orientation.

Claim 30

The invention according to Claim 25 wherein said first and second main electrode means extend in column form perpendicular to said rows, said first and second main electrode means extending parallel to each other in interdigitated manner by means of a plurality of terminal straps, each strap extending perpendicularly across said rows and being wide enough to straddle portions of adjacent cells in each row, each strap insulated above said gate electrode means, a given strap ohmically contacting a left hand oriented cell therebeneath in a first row and then ohmically contacting a right hand oriented cell therebeneath in the second row, and so on.

Claim 31

The invention according to Claim 2 4 wherein said substrate includes an epitaxial layer of predetermined depth into which said regions are formed, and wherein said insulative regions extend to a depth less than that of said expitaxial region but greater than that of said tub regions.