Split gate EFET

Claim 2

A bidirectional FET (102, Figures 12 & 13) comprising: a first source region (126) of one conductivity type semiconductor material; a first channel region (140) of opposite conductivity type semiconductor material forming a junction (138) with said first source region (126); a drift region (144) of said one conductivity type semiconductor material forming another junction (136) with said first channel region (140); a second channel region (142) of opposite conductivity type semiconductor material forming a junction (150) with said drift region (144); a second source region (128) of said one conductivity type semiconductor material forming a junction with said second channel region (142); and split gate electrode means (l12, 114) comprising a first gate electrode (112) disposed proximate said first channel region (140) and a second gate electrode (114) disposed proximate said second channel region (142), and adapted for application of an electrical potential for producing electric fields of sufficient intensity to invert the conductivity type in at least a portion of said first and second channel regions (140 and 142); whereby upon application of voltage of either polarity to said first and second source regions (126 and 128), electric current can flow in a respective corresponding direction between them, under control of said electrical potential of said split gate- electrode means (112, 114).

Claim 3

The invention according to Claim 1 wherein: said channel regions (140 and 142) are laterally spaced by said drift region (144) extending upwardly between said channel regions (140 and 142) to a top major surface (106) of said FET (102); said first gate electrode (112) extends laterally along said top major surface (106) and is spaced thereabove by a layer of insulation (110), said first gate electrode (112) extending across said first channel region (140); and said second gate electrode (114) extends laterally along said top major surface (106) and is spaced thereabove by a layer of insulation (110), said second gate electrode (114) extending across said second channel region (142) and laterally spaced from said first gate electrode (112).

Claim 4

The invention according to Claim 2 wherein said FET (102) has an OFF state in the absence of said electrical gate potential, with the junction (136) betwen said drift region (144) and one of said channel regions (140) blocking current flow toward one of said source regions (126) and with the junction (150) between said drift region (144) and the other of said channel regions (142) blocking current flow toward the other of said source regions (128), said laterally separated gate electrodes (112 and 114) affording high blocking voltage capability in said OFF state by preventing inversion of the conductivity type in said drift region (144) along said top major surface (106) between said channels (140 and 142).

Claim 5

The invention according to Claim 3 wherein said source regions (126 and 128) are laterally spaced along said top major surface (106), and wherein said channel regions (140 and 142) and said drift region (144) are disposed between said source regions (126 and 128).

Claim 6

The invention according to Claim 4 wherein said channel regions (140 and 142) are part of respective tub regions (118 and 120) of said opposite conductivity type extending laterally at least partially around respective said source regions (126 and 128), and comprising a pair of main electrodes (146 and 148) each connected to a respective said source region (126 or 128) and its respective tub region (118 or 120) to ohmically short each respective said source and channel region.

Claim 7

A bidirectional lateral power FET (102), comprising: a substrate (104) of semiconductor material of one conductivity type having a top major surface (106); a pair of channel regions (140 and 142) of the other conductivity type laterally spaced in said substrate (104) along said top major surface (106); a pair of source regions (126 and 128) of said one conductivity type each forming a junction with a respective one of said channel regions (140 and 142); a pair of main electrodes (146 and 148) connected respectively to said source regions (126 and 128); and split gate electrode means (112, 114) comprising first and second laterally separated gate electrodes (112 and 114) insulated above respective said first and second channel regions (140 and 142) for attracting given polarity carriers to invert said channel regions (140 and 142) to said one conductivity type in response to given gate potential, such that current may flow in either direction between said main electrodes (146 and 148).

Claim 8

A bidirectional lateral power FET (102), comprising: a substrate (104) of semiconductor material of one conductivity type having a top major surface (106); a pair of channel regions (140 and 142) of the other conductivity type laterally spaced in said substrate (104) along said top major surface (106); a pair of source regions (126 and 128) of said one conductivity type each forming a junction with a respective one of said channel regions (140 and 142); a pair of main electrodes (146 and 148) connected respectively to said source regions (126 and 128); and split gate electrode means (112, 114) comprising first and second laterally separated gate electrodes (112 and 114) insulated above respective said first and second channel regions (140 and 142) for attracting given polarity carriers to invert said channel regions (140 and 142) to said one conductivity type in response to given gate potential, such that current may flow in either direction between said main electrodes (146 and 148).

Claim 9

The invention according to Claim 6 wherein said channel regions (140 and 142) are spaced by said substrate (104) extending upwardly (144) between said channel regions (140 and 142) to said top major surface (106).

Claim 10

The invention according to Claim 7 wherein said source regions (126 and 128) are laterally spaced along said top major surface (106) with said channel regions (140 and 142) and said substrate (144) therebetween.

Claim 11

The invention according to Claim 8 wherein: said main electrodes (146 and 148) are connectable across an AC load line (154, 156); said split gate electrode means (112, 114) is connectable to gate potential means (160, Figure 12, or 172 and 174, Figure 13); such that at least one of said gate electrodes (112) is positive with respect to one of said main electrodes (146) during the first half cycle of said AC line, and such that at least the other of said gate electrodes (114) is positive with respect to the other of said main electrodes (148) during the second half cycle of said AC line; such that during the first half cycle of said AC line, current flows from said other main electrode (148) through the other said source region (128), through the other said channel region (142), through said upwardly extending portion (144) of said substrate (104), through said one channel region (140), through said one source region (126) to said one main electrode (146); and such that during the second half cycle of said AC line, current flows from said one main electrode (146) through said one source region (126), through said one channel region (140), through said upwardly extending portion (144) of said substrate (104), through said other channel region (142), through said other source region (128) to said other main electrode (148) .

Claim 12

The invention according to Claim 9 wherein said FET (102) has an OFF state in the absence of said given gate potential, with the junction (136) between said substrate (104) and one of said channel regions (140) blocking current flow toward the other of said main electrodes (146), and with the junction (150) between said substrate (104) and the other of said channel regions (142) blocking current flow toward the other of said main electrodes (148) .

Claim 13

The invention according to Claim 10 wherein said first and second gate electrodes (112 and 114) are connected in common to a gate terminal (158) which is connectable to a source of gate potential (160) in an on-gate condition and is . referenced to one of said main electrodes (146) in an off-gate condition.

Claim 14

The invention according to Claim 10 wherein said first and second gate electrodes (112 and 114) are each connectable to a source of gate potential (172 or 174, Figure 13) in an on-gate condition, and each referenced separately to a respective one of said main electrodes (146 or 148) in an off-gate condition.

Claim 15

The invention according to Claim 10 wherein: during said first half cycle of said AC line, current flows momentarily across a forward biased junction (150) between said other channel region (142) and said substrate (144), whereupon voltage between said main electrodes (146 and 148) drops and carriers are attracted toward the relative positive said other gate electrode (114) such that said other channel region (142) becomes conductive; and during said second half cycle of said AC line, current flows momentarily across a forward biased junction (136) between said one channel region (140) and said substrate (144), whereupon the voltage between said main electrodes (146 and 148) drops and carriers are attracted toward the relative positive said one gate electrode (112) such that said one channel region (140) becomes conductive.

Claim 16

The invention according to Claim 8 wherein: said channel regions (140 and 142) are part of respective tub regions (118 and 120) of said other conductivity type extending laterally at least partially around respective said source regions (126 and 128); and each said main electrode (146 or 148) is connected to both its respective said source region (126 or 128) and its respective said tub region (118 or 120) to ohmically short each respective said source and channel region.

Claim 17

The invention according to Claim 14 wherein: said main electrodes (146 and 148) are connectable across an AC load line (154, 156); said split gate electrode means (112, 114) is connectable to gate potential means (160, Figure 12, or 172 and 174, Figure 13); such that at least one of said gate electrodes (140) is positive with respect to one of said main electrodes (146) during the first half cycle of said AC line, and such that at least the other of said gate electrodes (142) is positive with respect to the other of said main electrodes (148) during the second half cycle of said AC line; such that during the first half cycle of said AC line, current flows from said other main electrode (148) through the other said source region (128), through the other said channel region (142), through said upwardly extending portion (144) of said substrate (104), through said one channel region (140), through said one source region (126) to said one main electrode (126); such that during the second half cycle of said AC line, current flows from said one main electrode (146) through said one source region (126), through said one channel region (140), through said upwardly extending portion (144) of said substrate (104), through said other channel region (142), through said other source region (128) to said other main electrode (148); and wherein said FET (102) has an OFF state in the absence of said given gate potential, with the junction between said substrate S(104) and one of said tub regions (118) blocking current flow toward one of said main electrodes (146), and with the junction (150) between said substrate (104) and the other of said tub regions (120) blocking current flow toward the other of said main electrodes (148).

Claim 18

The invention according to Claim 15 wherein: during said first half cycle of said AC line, current flows momentarily across a forward biased junction (150) between said other tub region (120) and said substrate (104), whereupon voltage between said main electrodes (146 and 148) drops and the section (152) in said other tub region (120) below said other channel region (142) becomes negative with respect to said other gate electrode (114), such that said other channel region (142) becomes conductive; and during said second half cycle of said AC line, current flows momentarily across a forward biased junction (136) between said one tub region (118) and said substrate (104), whereupon the voltage between said main electrodes (146 and 148) drops and the section of said one tub region (118) below said one channel region (140) becomes negative with respect to said one gate electrode (112), such that said one channel region (140) becomes conductive.

Claim 19

The invention according to Claim 16 wherein said tub regions (118 and 120) are initially formed in said substrate (104) and laterally spaced along said top major surface (106), followed by formation of said source regions (126 and 128) in respective said tub regions (118 and 120) to form said channel regions (140 and 142) along said top major surface (106) through said tub regions (118 and 120) between said source regions (1226 and 128) and said substrate (104).

Claim 20

The invention according to Claim 17 wherein said first and second gate electrodes (112 and 114) are connected in common to a gate terminal (158) which is connectable to a source of gate potential (160) in an on-gate condition and is referenced to one of said main electrodes (146) in an off-gate condition.

Claim 21

The invention according to Claim 17 wherein said first and second gate electrodes (112 and 114) are each connectable to a source of gate potential (172 and 174, Figure 13) in an on-gate condition, and each referenced separately to a respective one of said main electrodes (146 and 148) in an off-gate condition.

Claim 22

A bidirectional lateral power FET (102), comprising: a substrate (104) of semiconductor material having a top major surface (106) and including a lateral n epitaxial layer (104) extending downwardly from said top major surface (106) to at least a predetermined depth; at least first and second spaced apart p type regions (118 and 120) in said lateral n epitaxial layer (104), each extending downwardly from said top major surface (106) to a predetermined depth and laterally to a first junction (136 and 150) with said lateral n epitaxial layer (104); an n type region (126 and 128) embedded in each of said p type regions (118 and 120) at said top major surface (106) , each said n type region (126 and 128) extending downwardly into its respective p type region (118 and 120) to a predetermined depth and laterally to a second junction formed with each of said p type regions (118 and 120) respectively, so as to define a FET channel region (140 and 142) between said first and second junctions for each of said spaced apart regions; split gate electrode means (112, 113) comprising first and second electrically conductive gate electrodes (112 and 114) above said channel regions (140 and 142) adapted for application of electrical potential, for producting controllable electric fields in said channel regions (140 and 142); insulation means (110) disposed intermediate said gate electrode means (112, 114) and said channel regions (140, 142) for preventing current flow therebetween; a pair of main electrode means (146 and 148) each conductively communicating with a respective one of said embedded n type regions (126 and 128) for serving as an electron current source when a negative voltage is applied to one of said main electrode means relative to the voltage on the other of said main electrode means, and serving as a anode when a positive voltage is applied to said one main electrode means relative to the voltage on said other main electrode means; whereby upon application of voltage of either polarity to said main electrode means (146 and 148) current flow in either direction between said spaced apart regions is controllable by controlling said potential on said gate electrode means (112 and 114).

Claim 23

A bidirectional lateral power FET (102), comprising: a substrate (104) of semiconductor material having a top major surface (106) and including a lateral n epitaxial layer (104) extending downwardly from said top major surface (106) to at least a predetermined depth; at least first and second spaced apart p type regions (118 and 120) in said lateral n epitaxial layer (104), each extending downwardly from said top major surface (106) to a predetermined depth and laterally to a first junction (136 and 150) with said lateral n epitaxial layer (104); an n type region (126 and 128) embedded in each of said p type regions (118 and 120) at said top major surface (106) , each said n type region (126 and 128) extending downwardly into its respective p type region (118 and 120) to a predetermined depth and laterally to a second junction formed with each of said p type regions (118 and 120) respectively, so as to define a FET channel region (140 and 142) between said first and second junctions for each of said spaced apart regions; split gate electrode means (112, 113) comprising first and second electrically conductive gate electrodes (112 and 114) above said channel regions (140 and 142) adapted for application of electrical potential, for producting controllable electric fields in said channel regions (140 and 142); insulation means (110) disposed intermediate said gate electrode means (112, 114) and said channel regions (140, 142) for preventing current flow therebetween; a pair of main electrode means (146 and 148) each conductively communicating with a respective one of said embedded n type regions (126 and 128) for serving as an electron current source when a negative voltage is applied to one of said main electrode means relative to the voltage on the other of said main electrode means, and serving as a anode when a positive voltage is applied to said one main electrode means relative to the voltage on said other main electrode means; whereby upon application of voltage of either polarity to said main electrode means (146 and 148) current flow in either direction between said spaced apart regions is controllable by controlling said potential on said gate electrode means (112 and 114).

Claim 24

The invention according to Claim 20 wherein said FET (102) has an OFF state in the absence of said electrical gate potential, with the junction (136) between said n epitaxial layer (104) and said first p type region (118) blocking current flow toward one of said main electrode means (146), and with the junction (150) between said n epitaxial layer (104) and said second p type region (120) blocking current flow toward the other of said main electrode means (148), said first and second gate electrodes (112 and 114) being laterally spaced along said top major surface (106) and affording high blocking voltage capability in said OFF state by preventing inversion of the conductivity type in said n epitaxial layer (104, 170) along said top major surface (106) between said spaced apart p type regions (118 and 120).

Claim 25

The invention according to Claim 21 wherein: said main electrode means (146 and.148) are connectable-across an AC load line (154, 156); said split gate electrode means (112, 114) is connectable to gate potential means (160, Figure 12, or 172 and 174, Figure 13); such that at least one of said gate electrodes (112) is positive with respect to one of said main electrodes (146) means during the first half cycle of said AC line, and such that at least the other of said gate electrodes (114) is positive with respect to the other of said main electrode means (148) during the second half cycle of said AC line; such that during the first half cycle of said AC line, current flows from said other main electrode means (148) through the other of said n type regions (128), through the other said channel region (142) through a section (144) of said n epitaxial layer (104) extending upwardly between said p type regions (118 and 120) to said top major surface (106), through said one channel region (140) through the one said n type region (126) to said one main electrode means (146); and such that during the second half cycle of said AC line, current flows from said one main electrode means (146) through said one n type region (126), through said one channel region (140), through said upwardly extending section (144) of said n epitaxial layer (104, through said other channel region (142), through said other n type region (128) to said other main electrode means (148).

Claim 26

A bidirectional FET (102) comprising: a semiconductor body (104) of one conductivity type having a top major surface (106); a first structure in said semiconductor body comprising: a first region (118) of opposite conductivity type having a portion extending from a first predetermined depth to a second greater predetermined depth below said top major surface (106) of said semiconductor body (104) and having another portion extending upwardly towards said top major surface (106) to serve as a first FET channel (140); and a first region (126) of said one conductivity type in said first region (118) of said opposite conductivity type and extending from said top major surface (106) of said semiconductor body (104) into said body to said first predetermined depth and extending laterally to form a junction (138) with said upwardly extending portion (140) of said first region (118) of said opposite conductivity type; first main electrode means (146) for contacting said first region (126) of said one conductivity type; a second structure in said semiconductor body comprising: a second region (120) of said opposite conductivity type having a portion extending from a first predetermined depth to a second greater predetermined depth below said-top major surface (106) of said semiconductor body (104), and having another portion extending upwardly towards said top major surface (106) to serve as a second FET channel (142); and a second region (128) of said one conductivity type in said second region (120) of said opposite conductivity type and extending from said top major surface (106) of said semiconductor body (104) into said body to said first predetermined depth and extending laterally to form a junction with said upwardly extending portion (142) of said second region (120) of said opposite conductivity type; second main electrode means (148) for contacting said second region (128) of said one conductivity type; insulating means (110) overlying said semiconductor body (104) atop said FET channels (140 and 142); split gate electrode means (112, 114) comprising a first gate electrode (112) overlying said insulating means (110) above said first FET channel (140) and a second gate electrode (114) overlying said insulating means (110) above said second FET channel (142) and adapted for application of electrical potential for producting electric fields in said FET channels (140 and 142); whereby when voltage of either polarity is ' applied between said first and second main electrode means (146 and 148), the potential of said gate electrode means (112 and 114) controls the flow of current, in a direction corresponding respectively to said voltage polarity, from one to the other of said main electrode means (146 and 148), by electric fields effective in said FET channels (140 and 142); said split first and second gate electrodes (140 and 142) preventing conductivity inversion in said semiconductor body (104, 170) along said top major surface (106) in an OFF state of said FET (102).

Claim 27

A bidirectional FET (102) comprising: a semiconductor body (104) of one conductivity type having a top major surface (106); a first structure in said semiconductor body comprising: a first region (118) of opposite conductivity type having a portion extending from a first predetermined depth to a second greater predetermined depth below said top major surface (106) of said semiconductor body (104) and having another portion extending upwardly towards said top major surface (106) to serve as a first FET channel (140); and a first region (126) of said one conductivity type in said first region (118) of said opposite conductivity type and extending from said top major surface (106) of said semiconductor body (104) into said body to said first predetermined depth and extending laterally to form a junction (138) with said upwardly extending portion (140) of said first region (118) of said opposite conductivity type; first main electrode means (146) for contacting said first region (126) of said one conductivity type; a second structure in said semiconductor body comprising: a second region (120) of said opposite conductivity type having a portion extending from a first predetermined depth to a second greater predetermined depth below said-top major surface (106) of said semiconductor body (104), and having another portion extending upwardly towards said top major surface (106) to serve as a second FET channel (142); and a second region (128) of said one conductivity type in said second region (120) of said opposite conductivity type and extending from said top major surface (106) of said semiconductor body (104) into said body to said first predetermined depth and extending laterally to form a junction with said upwardly extending portion (142) of said second region (120) of said opposite conductivity type; second main electrode means (148) for contacting said second region (128) of said one conductivity type; insulating means (110) overlying said semiconductor body (104) atop said FET channels (140 and 142); split gate electrode means (112, 114) comprising a first gate electrode (112) overlying said insulating means (110) above said first FET channel (140) and a second gate electrode (114) overlying said insulating means (110) above said second FET channel (142) and adapted for application of electrical potential for producting electric fields in said FET channels (140 and 142); whereby when voltage of either polarity is ' applied between said first and second main electrode means (146 and 148), the potential of said gate electrode means (112 and 114) controls the flow of current, in a direction corresponding respectively to said voltage polarity, from one to the other of said main electrode means (146 and 148), by electric fields effective in said FET channels (140 and 142); said split first and second gate electrodes (140 and 142) preventing conductivity inversion in said semiconductor body (104, 170) along said top major surface (106) in an OFF state of said FET (102).

Claim 28

The invention according to Claim 23 wherein said main electrode means (146 and 148) are connectable across an AC load line (154, 156); said split gate electrode means (112 and 114) is connectable to gate potential means (160, Figure 12, or 172 and 174, Figure 13) in an on-gate condition, and is referenced to at least one of said main electrode means in an off-gate condition; said first and second gate electrodes (112 and 114) being laterally spaced and preventing undesiredinducement of conduction channels through said semiconductor body (104) between said FET channels (140 and 142) in said OFF state of said FET (102A) while still allowing said common referencing to the potential level of at least one of said main electrode means.

Claim 29

A bidirectional lateral FET (102) on a semiconductor body (104) comprising: a first source region (126); a common drain region (144); a first channel region (140) between said first source region (126) and said common drain region (144); a second source region (128); a second channel region (142) between said second source region (128) and said common drain region (144); said first channel region (140) and said common drain region (144) being contiguous to define a first interface (136) therebetween; said second channel region (142) and said common drain region (144) being contiguous to define a second interface (150) therebetween; split gate electrode means (112,114) comprising a first gate electrode (112) proximate said first channel region (140) and a laterally spaced second gate electrode (114) proximate said second channel region (142) for controllably inducing electric fields in said channel regions (140 and 142); insulating means (110) between said gate electrode means (112 and 114) and said first and second channel regions (140 and 142) for electrically insulating said gate electrode means (112 and 114) from said first and second channel regions (140 and 142); whereby when a voltage is applied to said first source region (126) which is negative with respect to said second source region (128), electron flow from said first source region (126) to said second source region (128) is controllable by controlling voltage applied to said gate electrode means (112, 114). and when a voltage is applied to said second source region (128) which is negative with respect to said first source region (126), electron flow from said second source region (128) to said first source region (126) is controllable by controlling voltage applied to said gate electrode means (112, 114).

Claim 30

A bidirectional lateral FET (102) on a semiconductor body (104) comprising: a first source region (126); a common drain region (144); a first channel region (140) between said first source region (126) and said common drain region (144); a second source region (128); a second channel region (142) between said second source region (128) and said common drain region (144); said first channel region (140) and said common drain region (144) being contiguous to define a first interface (136) therebetween; said second channel region (142) and said common drain region (144) being contiguous to define a second interface (150) therebetween; split gate electrode means (112,114) comprising a first gate electrode (112) proximate said first channel region (140) and a laterally spaced second gate electrode (114) proximate said second channel region (142) for controllably inducing electric fields in said channel regions (140 and 142); insulating means (110) between said gate electrode means (112 and 114) and said first and second channel regions (140 and 142) for electrically insulating said gate electrode means (112 and 114) from said first and second channel regions (140 and 142); whereby when a voltage is applied to said first source region (126) which is negative with respect to said second source region (128), electron flow from said first source region (126) to said second source region (128) is controllable by controlling voltage applied to said gate electrode means (112, 114). and when a voltage is applied to said second source region (128) which is negative with respect to said first source region (126), electron flow from said second source region (128) to said first source region (126) is controllable by controlling voltage applied to said gate electrode means (112, 114).

Claim 31

The invention according to Claim 25 wherein electron flow from said first source region (126) to said second source region (128) is controllable by controlling the voltage applied to said first gate electrode (112), and wherein electron flow from said second source region (128) to said first source region (126) is controllable by controlling the voltage applied to said second gate electrode (114).

Claim 32

A bidirectional laterally integrated power switching plural FET structure (202, Figures 14-16), comprising: a substrate (214) of semiconductor material of one conductivity type having a top major surface (244); a first tub region (218) of the other conductivity type in said substrate (214) along said top major surface (244) ; first and second source region portions (226) of said one conductivity type in said first tub region (218) laterally spaced along said top major surface (244); a second tub region (220) of said other conductivity type in said substrate (214) laterally spaced from said first tub region (218) along said top major surface (244) ; third and fourth source region portions (228) of said one conductivity type in said second tub region (220) laterally spaced along said top major surface (244); third, fourth and so on, tub regions (222) in said substrate (214) having fifth and sixth, seventh and eighth, and so on, source region portions (230); a first gate electrode (208a) insulatingly spaced above said top major surface (244) and extending across the section (254) of said first tub region (218) between said second source region portion (226) and said substrate (214, 256); a second gate electrode (210a) insulatingly spaced above said top major surface (244) and extending across the section (260) of said second tub region (220) between said substrate (214, 256) and said third source region portion (228); a third gate electrode (208a) insulatingly spaced above said top major surface (244) and extending across the section (272) of said second tub region(220) between said fourth source region portion (228) and said substrate (214); a fourth gate electrode (210a) insulatingly spaced above said top major surface (244) and extending across the section of said third tub region (222) between said substrate (214) and said fifth source region portion (230); fifth, sixth, and so on, gate electrodes; a first main electrode (204a) ohmically connected to said first and second source region portions (226) and the section (238) of said first tub region (218) therebetween; a second main electrode (206a) ohmically connected to said third and fourth souce region portions (228) and the section (240) of said second tub region (220) therebetween; third, fourth, and so on, main electrodes; said section (254) of said first tub region (218) between said second source region portion (226) and said substrate (214, 256) comprising a first channel region (254) along said top major surface (244), and said section (260) of said second tub region (220) between said substrate (214, 256) and said third source region portion (228) comprising a second channel region (260) along said top major surface (244), such that given gate potential on said first and second gate electrodes (208a and 210a) attracts given polarity carriers to invert said first and second channel regions (254 and 260) to said one conductivity type such that current may flow in either direction between said first and second main electrodes (204a and 206a); said section (272) of said second tub region (220) between said fourth source region portion (228) and said substrate (214) comprising a third channel region (272) and said section of said third tub region(222) between said substrate (214) and said fifth source region portion (230) comprising a fourth channel region, such that given gate potential on said third and fourth gate electrodes (208a and 210a) attracts said given polarity carriers and inverts said third and fourth channel regions to said one conductivity type such that current may flow in either direction between said second and third main electrodes, and so on.

Claim 33

A bidirectional laterally integrated power switching plural FET structure (202, Figures 14-16), comprising: a substrate (214) of semiconductor material of one conductivity type having a top major surface (244); a first tub region (218) of the other conductivity type in said substrate (214) along said top major surface (244) ; first and second source region portions (226) of said one conductivity type in said first tub region (218) laterally spaced along said top major surface (244); a second tub region (220) of said other conductivity type in said substrate (214) laterally spaced from said first tub region (218) along said top major surface (244) ; third and fourth source region portions (228) of said one conductivity type in said second tub region (220) laterally spaced along said top major surface (244); third, fourth and so on, tub regions (222) in said substrate (214) having fifth and sixth, seventh and eighth, and so on, source region portions (230); a first gate electrode (208a) insulatingly spaced above said top major surface (244) and extending across the section (254) of said first tub region (218) between said second source region portion (226) and said substrate (214, 256); a second gate electrode (210a) insulatingly spaced above said top major surface (244) and extending across the section (260) of said second tub region (220) between said substrate (214, 256) and said third source region portion (228); a third gate electrode (208a) insulatingly spaced above said top major surface (244) and extending across the section (272) of said second tub region(220) between said fourth source region portion (228) and said substrate (214); a fourth gate electrode (210a) insulatingly spaced above said top major surface (244) and extending across the section of said third tub region (222) between said substrate (214) and said fifth source region portion (230); fifth, sixth, and so on, gate electrodes; a first main electrode (204a) ohmically connected to said first and second source region portions (226) and the section (238) of said first tub region (218) therebetween; a second main electrode (206a) ohmically connected to said third and fourth souce region portions (228) and the section (240) of said second tub region (220) therebetween; third, fourth, and so on, main electrodes; said section (254) of said first tub region (218) between said second source region portion (226) and said substrate (214, 256) comprising a first channel region (254) along said top major surface (244), and said section (260) of said second tub region (220) between said substrate (214, 256) and said third source region portion (228) comprising a second channel region (260) along said top major surface (244), such that given gate potential on said first and second gate electrodes (208a and 210a) attracts given polarity carriers to invert said first and second channel regions (254 and 260) to said one conductivity type such that current may flow in either direction between said first and second main electrodes (204a and 206a); said section (272) of said second tub region (220) between said fourth source region portion (228) and said substrate (214) comprising a third channel region (272) and said section of said third tub region(222) between said substrate (214) and said fifth source region portion (230) comprising a fourth channel region, such that given gate potential on said third and fourth gate electrodes (208a and 210a) attracts said given polarity carriers and inverts said third and fourth channel regions to said one conductivity type such that current may flow in either direction between said second and third main electrodes, and so on.

Claim 34

The invention according to Claim 27 comprising: first gate terminal means (208) ohmically interconnecting said first, third, fifth, and so on gate electrodes (208a); second gate terminal means (210) ohmically interconnecting said second, fourth, and so on gate electrodes (210a); first main terminal means (204) ohmically interconnecting said first, third, fifth, and so on main electrodes (204a); and second main terminal means (206) ohmically interconnecting said second, fourth, and so on main electrodes (206a).

Claim 35

The invention according to Claim 28 wherein: said first and second main terminal means (204 and 206) are connectable across an AC load line (154, 156); said gate terminal means (208, 210) is connectable to gate potential means (160, Figure 12, or 172 and 174, Figure 13); such that at least said first gate terminal means (208) is positive with respect to said first main terminal means (204) during the first half cycle of said AC line, and such that at least said second gate terminal means (210) is positive with respect to said second main terminal means (206) during the second half cycle of said AC line; such that during the first half cycle of said AC line, current flows from said second main terminal means (206) through the odd numbered of said source regions, through the even numbered of said channel regions, through the sections of said substrate extending upwardly to said top major surface between said tub regions, through the odd numbered of said channel regions, through the even numbered of said source regions to said first main terminal means (204); and such that during the second half cycle of said AC line, current flows from said first main terminal means (204) through the even numbered of said source regions, through the odd numbered of said channel regions, through said upwardly extending portions of said substrate between said tub regions, through the even numbered of said channel regions, through the odd numbered of said source regions to said second main terminal means (206).

Claim 36

The invention according to Claim 29 wherein said FET (202) has an OFF state in the absence of said given gate potential, with the junctions between said substrate and said tub regions along the odd numbered of said channel regions blocking current flow toward said first main terminal means (204), and with the junctions between said substrate and said tub regions along the even numbered of said channel regions blocking current flow toward said second main terminal means (206). said gate electrodes (208a, 210a) being laterally separated along said top major surface (244) and affording high blocking capability in said OFF state by preventing inversion of the conductivcity type in said upwardly extending sections of said substrate (214) along said top major surface (244) between said tub regions.

Claim 37

The invention according to Claim 30 wherein said first and second gate terminal means (208 and 210) are connected in common to a common gate terminal (158) which is connectable to a source of gate potential (160) in an on-gate condition and is referenced to one of said main terminal means in an off-gate condition.

Claim 38

The invention according to Claim 30 wherein said first and second gate terminal means (208 and 210) are each connectable to a source of gate potential (172 and 174) in an on-gate condition and each referenced separately to a respective one of said main terminal means (204 and 208) in an off-gate condition.

Claim 39

An integrated plural lateral FE T structure (202, Figures 14-16) for bidirectional power switching, comprising: a semiconductor chip (202) comprising a substrate (214) of one conductivity type; a plurality of laterally spaced cells (218a, 220a, 222a) forming a matrix array on said substrate (214) along a top major surface (244) thereof; each said cell (218a, 220a, 222a) having a right-hand portion (227, 221) forming a lateral FET (264, 262) in combination with the left-hand portion (225, 223) of the next adjacent cell to the right; each cell (218a, 220a, 222a) having a left-hand portion (225, 223) forming a lateral FET (264, 262) combination with the right-hand portion (227, 221) of the next adjacent cell to the left; each cell (such as 220a) comprising; a tub region (220) of opposite conductivity type in said substrate (214) and extending laterally and then upwardly to said top major surface (244) to form right and left boundaries (266 and 258) defining right and left junctions (266 and 258) with said substrate (214); source region means (228) of said one conductivity type in said tub region (220) and having right and left portions extending laterally and then upwardly to said top major surface (244) to define right and left junctions (270 and 268) with said right and left upward extentions (272 and 260) of said tub region (220); said right and left upward extentions (272 and 260) of said tub region (220) forming right and left FET channels (272 and 260) immediately below said top major surface (244) ; said right and left source region portions (228) also extending laterally towards each other and then upwardly to said top major surface (244) such that an intermediate portion (240) of said tub region (220) extends upwardly to said top major surface (244) between said right and left source region portions (228); first main electrode means (206a) ohmically interconnecting said upwardly extending intermediate tub region portion (240) at said top major surface (244) with the intermediate tub region portion of alternate cells; second main electrode means (204a) ohmically interconnecting said upwardly extending intermediate tub region portions of the remaining alternate cells;

Claim 40

An integrated plural lateral FE T structure (202, Figures 14-16) for bidirectional power switching, comprising: a semiconductor chip (202) comprising a substrate (214) of one conductivity type; a plurality of laterally spaced cells (218a, 220a, 222a) forming a matrix array on said substrate (214) along a top major surface (244) thereof; each said cell (218a, 220a, 222a) having a right-hand portion (227, 221) forming a lateral FET (264, 262) in combination with the left-hand portion (225, 223) of the next adjacent cell to the right; each cell (218a, 220a, 222a) having a left-hand portion (225, 223) forming a lateral FET (264, 262) combination with the right-hand portion (227, 221) of the next adjacent cell to the left; each cell (such as 220a) comprising; a tub region (220) of opposite conductivity type in said substrate (214) and extending laterally and then upwardly to said top major surface (244) to form right and left boundaries (266 and 258) defining right and left junctions (266 and 258) with said substrate (214); source region means (228) of said one conductivity type in said tub region (220) and having right and left portions extending laterally and then upwardly to said top major surface (244) to define right and left junctions (270 and 268) with said right and left upward extentions (272 and 260) of said tub region (220); said right and left upward extentions (272 and 260) of said tub region (220) forming right and left FET channels (272 and 260) immediately below said top major surface (244) ; said right and left source region portions (228) also extending laterally towards each other and then upwardly to said top major surface (244) such that an intermediate portion (240) of said tub region (220) extends upwardly to said top major surface (244) between said right and left source region portions (228); first main electrode means (206a) ohmically interconnecting said upwardly extending intermediate tub region portion (240) at said top major surface (244) with the intermediate tub region portion of alternate cells; second main electrode means (204a) ohmically interconnecting said upwardly extending intermediate tub region portions of the remaining alternate cells;

Claim 41

split gate electrode means (208a, 210a) insulated above said top major surface (244) of said substrate (214) in a waffle-like pattern, comprising a first gate electrode (208a) overlying and extending across said right FET channel of a left cell, and a second gate electrode (210a) laterally spaced from said first gate electrode (208a) and extending across said left FET channel of a right cell, said upwardly extending portion of said substrate (214) beneath said gate electrode means (208a, 210a) likewise forming a waffle-like pattern separating the rows and columns of said cells in said matrix array.

Claim 42

split gate electrode means (208a, 210a) insulated above said top major surface (244) of said substrate (214) in a waffle-like pattern, comprising a first gate electrode (208a) overlying and extending across said right FET channel of a left cell, and a second gate electrode (210a) laterally spaced from said first gate electrode (208a) and extending across said left FET channel of a right cell, said upwardly extending portion of said substrate (214) beneath said gate electrode means (208a, 210a) likewise forming a waffle-like pattern separating the rows and columns of said cells in said matrix array.

Claim 43

The invention according to Claim 33 wherein said upwardly extending intermediate tub region portion (240) is offset to the right or left of center in said cells such that said main electrode (206a) connection point is likewise offset to the right or left in each cell; in a first row of cells (274), each cell having said main electrode connection point to the left of center to thus have a left-hand orientation. in the second row of cells (276), each cell having said main electrode connection point to the right of center to thus have a right-hand orientation.

Claim 44

The invention according to Claim 34 wherein said first and second main electrode means (204a and 206a) extend in column form perpendicular to said rows, said first and second main electrode means (204a and 206a) extending parallel to each other in interdigitated manner by means of a plurality of terminal straps (Tl and T2), each strap extending perpendicularly across said rows and being wide enough to straddle portions of adjacent cells in each row, each strap (Tl and T2) insulated above said gate electrode means (208a and 210a), a given strap ohmically contacting a left-hand oriented cell therebeneath in a first row and then ohmically contacting a right-hand oriented cell therebeneath in the second row, and so on.