Patent EP0194031A1 successfully refreshed from Google Patents.
EP0194031A1
Expired / Lapsed
EP
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CMOS bandgap reference voltage circuits
Assignee: AT&T Inc
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Filing: 1986-02-03
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Granted: —
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Expires: 2006-02-03
Abstract
Abstract A CMOS bandgap voltage reference which is temperature stable is disclosed. The large temperature-dependent p-tub resistors of prior art arrangements are replaced with relatively small, temperature stable p+ diffusion resistors (32, 34). The increase in current level needed to compensate for the decrease in resistor value is provided by a simple cascode MOS circuit (36) located between the ratioing resistors and the VSS potential.
Inventors
- 👤 Donald Allan Kerth
- 👤 Navdeep Singh Sooch
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 15:50
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/30; Y; Y10; Y10S; Y10S323/00; Y10S323/907
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
326 words
A voltage reference circuit (30) for providing as an output a bandgap reference voltage (V BG ) which is substantially independent of temperature, the reference circuit including differential amplifying means (16), a first bipolar transistor (12) having its collector and base connected to a first reference potential point (V DD ), a second bipolar transistor (14) having its collector and base connected to the first reference potential point, and characterised in that the emitter of the second bipolar transistor is connected to a first input terminal of the differential amplifying means, a first resistor (32) is connected between the emitter of the first transistor and a second input terminal of the differential amplifying means, a second resistor (34) is connected to the emitter of the second bipolar transistor, and there is provided an MOS cascode transistor arrangement (36) connected serially between the first and second resistors and a second reference potential point (V SS ) and further connected to an output terminal of the differential amplifying means, the MOS cascode transistor arrangement including a first plurality of MOS transistors (40,42) each MOS transistor having a source, drain and gate terminal and formed to comprise a width-to-length ratio defined as Z/L, the first plurality of MOS transistors being connected between the first resistor and the second reference potential point, and a second plurality of MOS transistors (44,46), each MOS transistor having a source, drain and gate terminal and formed to comprise a width-to-length ratio defined as n(Z/L), n being defined as a width-to-length size factor, the second plurality of MOS transistor being connected between the second resistor and the second reference potential point, the voltage reference circuit serving to provide the output bandgap reference voltage which is proportional to the sum of the base-to-emitter voltage of the first transistor and the ratio of the second and first resistors multiplied by both the size factor n and the difference in base-to-emitter voltages of the first and second transistors.
Claim 2
Dependent Claim
326 words
A voltage reference circuit (30) for providing as an output a bandgap reference voltage (V BG ) which is substantially independent of temperature, the reference circuit including differential amplifying means (16), a first bipolar transistor (12) having its collector and base connected to a first reference potential point (V DD ), a second bipolar transistor (14) having its collector and base connected to the first reference potential point, and characterised in that the emitter of the second bipolar transistor is connected to a first input terminal of the differential amplifying means, a first resistor (32) is connected between the emitter of the first transistor and a second input terminal of the differential amplifying means, a second resistor (34) is connected to the emitter of the second bipolar transistor, and there is provided an MOS cascode transistor arrangement (36) connected serially between the first and second resistors and a second reference potential point (V SS ) and further connected to an output terminal of the differential amplifying means, the MOS cascode transistor arrangement including a first plurality of MOS transistors (40,42) each MOS transistor having a source, drain and gate terminal and formed to comprise a width-to-length ratio defined as Z/L, the first plurality of MOS transistors being connected between the first resistor and the second reference potential point, and a second plurality of MOS transistors (44,46), each MOS transistor having a source, drain and gate terminal and formed to comprise a width-to-length ratio defined as n(Z/L), n being defined as a width-to-length size factor, the second plurality of MOS transistor being connected between the second resistor and the second reference potential point, the voltage reference circuit serving to provide the output bandgap reference voltage which is proportional to the sum of the base-to-emitter voltage of the first transistor and the ratio of the second and first resistors multiplied by both the size factor n and the difference in base-to-emitter voltages of the first and second transistors.
Claim 3
Dependent Claim
159 words
A circuit as claimed in claim 1 wherein the MOS cascode transistor arrangement includes a first (40) and a second (42) MOS transistor, forming the first plurality of MOS transistors, connected in series between the first resistor and the second reference potential point, the gate terminal of the first MOS transistor being connected to the output of the differential amplifying means and the gate of the second MOS transistor being connected to the interconnection of the source of the first MOS transistor and the drain of the second MOS transistor, and a third (44) and a fourth (46) MOS transistor, forming the second plurality of MOS transistors, connected in series between the second resistor and the second reference potential point, the gate terminal of the third MOS transistor being connected to the gate terminal of the first MOS transistor and the gate terminal of the fourth MOS transistor being connected to the gate terminal of the second MOS transistor.
Claim 4
Dependent Claim
95 words
A circuit as claimed in claim 2 including a fifth MOS transistor (50) for providing a reference current, the gate of the fifth MOS transistor being connected to the interconnected gates of the second and fourth MOS transistors and the source of the fifth MOS transistor-being connected to the second reference potential point, the fifth MOS transistor having a width-to-length of m(Z/L) and being for providing a-drain current as the reference current related to the ratio of m and the first resistor multiplied by a constant value related to the first and second bipolar transistors.
Claim 5
Dependent Claim
54 words
A circuit as claimed in claim 2 including an MOS cascode current mirror (62,64,66,68) connected between the first and second reference potential points and connected to the cascode MOS transistor arrangement for biasing the cascode MOS transistor arrangement at a predetermined value which decreases the voltage difference between the first and second reference potentials.
References Cited (Backward Citations)
US4287439A
Cited
US4380706A
Cited
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