EP0184016A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Heterojunction bipolar transistor
Assignee: Hitachi Ltd
•
Filing: 1985-11-06
•
Granted: —
•
Expires: 2005-11-06
Abstract
Abstract A collector lead-out portion (22) and a base lead-out portion (14) are formed so as to oppose each other in such a manner that active regions including a collector (3), a base (2) and an emitter (1) are sandwiched therebetween. The collector lead-out portion (22) and the base lead-out portion (14) are formed by ion implantation or selective epitaxial growth. Thus, a planar type heterojunction bipolar transistor capable of a high density of integration is formed.
Inventors
- 👤 Kiichi Ueyanagi
- 👤 Susumu Takahashi
- 👤 Toshiyuki Usagawa
- 👤 Yasunari Umemoto
- 👤 Toshihisa Tsukada
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 09:06
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/113; H10D10/00; H10D10/80; H10D10/821; H10D64/00; H10D64/20; H10D64/23; H10D64/231; H10D64/27; H10D64/281
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
59 words
A heterojunction bipolar transistor comprising active regions (1, 2, 3) which include at least one heterojunction, a base region lead-out portion (14) which is formed by the side of said active regions through an insulating region (19), and a collector region lead-out portion (22) which is formed by the side of said active regions through an insulating region (23).
Claim 2
Dependent Claim
59 words
A heterojunction bipolar transistor comprising active regions (1, 2, 3) which include at least one heterojunction, a base region lead-out portion (14) which is formed by the side of said active regions through an insulating region (19), and a collector region lead-out portion (22) which is formed by the side of said active regions through an insulating region (23).
Claim 3
Dependent Claim
32 words
A heterojunction bipolar transistor according to claim 1, wherein said collector region lead-out portion (22) is formed in opposition to said base region lead-out portion (14) with said active regions interposed therebetween.
Claim 4
Dependent Claim
49 words
A heterojunction bipolar transistor according to claim 1, wherein a surface of a semiconductor substrate (11) which is a parent material constructing said heterojunction bipolar transistor is substantially flat, and an emitter electrode (13), a base electrode (15) and a collector electrode (16) are formed on the flat surface.
Claim 5
Dependent Claim
26 words
A heterojunction bipolar transistor according to claim 3, wherein said collector lead-out portion (22) is an impurity containing region which is formed by ion implantation (27).
Claim 6
Dependent Claim
54 words
A heterojunction bipolar transistor according to claim 4, wherein said collector lead-out portion (22) is an impurity containing region which is formed by ion implantation, and the ion implantation is so performed that a peak of an impurity concentration reaches a depth corresponding substantially to the base region (2) of said heterojunction bipolar transistor.
Claim 7
Dependent Claim
19 words
A heterojunction bipolar transistor according to claim 4, wherein said impurity containing region (22) is of the n-conductivity type.
Claim 8
Dependent Claim
22 words
A heterojunction bipolar transistor according to claim 3, wherein said collector lead-out portion (22) is constructed of a selectively grown semiconductor layer.
Claim 9
Dependent Claim
41 words
A heterojunction bipolar transistor according to claim 3, wherein said active regions (1, 2, 3) are isolated from said base lead-out portion (14) and said collector lead-out portion (22) by damaged regions (19, 23) which are formed by impurity ion implantation.
Claim 10
Dependent Claim
34 words
A heterojunction bipolar transistor according to claim 8, wherein the ion-implanted region (19, 23) for the isolation between said active regions and said collector lead-out portion is formed deeper than the base region (2).
Claim 11
Dependent Claim
44 words
A heterojunction bipolar transistor according to claim 9, wherein the isolation region (19, 23) between said active regions (1, 2, 3) and said collector lead-out portion (22) as well as said base lead-out portion (14) is formed in self-alignment to said emitter electrode (13).
Claim 12
Dependent Claim
31 words
A heterojunction bipolar transistor according to claim 3 or 4, wherein said collector lead-out portion (22) and said base lead-out portion (14) are formed in self-alignment to said emitter electrode (13).
Claim 13
Dependent Claim
62 words
A heterojunction bipolar transistor according to claim 3 or 8, wherein an isolation region (19) between said active regions (1, 2, 3) and said base region lead-out portion (14) is formed at a depth at which it reaches a depletion layer (50) on an emitter side to be formed at an interface between the emitter layer (1) and the base layer (2).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.