Patent EP0174236A1 successfully refreshed from Google Patents.
EP0174236A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor integrated circuit device having a test circuit
Assignee: Fujitsu Ltd
•
Filing: 1985-08-02
•
Granted: —
•
Expires: 2005-08-02
Abstract
Abstract A semiconductor integrated circuit device having a test circuit including a plurality of gate cells (2) arranged in a matrix; wiring for connecting the gate cells so as to constitute a logic circuit; a plurality of row selection wires (3) provided along the gate cells in a row direction, each of the gate cells (2) being operatively connected to a row selection wire (3) a plurality of a column read-out wires (4) provided along the gate cells in a column direction, outputs of each of the gate cells (2) being operatively connected to column read-out wires (4), a row selection ring counter (6), operatively connected to the row selection wires (3), for selecting any of the row selection wires (3) and for the selecting of any of the gate cells (2) connected to the selected row selection wire (3); and a data selector (8) and ring counter (7) for reading out of the gate cells (2) arranged in the logic circuits through the column read-out wires (4). Figure 1.
Inventors
- 👤 Osam Ohba
- 👤 Makoto Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 14:27
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/20; G01L; G01L27/00; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
142 words
A semiconductor integrated circuit device having a test circuit comprising: a plurality of gate cells arranged in a matrix; wiring means for connecting the gate cells so as to constitute a logic circuit; a plurality of row selection wires provided along said gate cells in a row direction, each of said gate cells being operatively connected to said row selection wire; a plurality of column read-out wires provided along said gate cells in a column direction, outputs of each of said gate cells being operatively connected to column read-out wires; row selection means, operatively connected to said row selection wires, for selecting any of said row selection wires and for selecting any of said gate cells connected to said selected row selection wire, and output means for reading out said gate cells arranged in said logic circuit through a column read-out wire.
Claim 2
Dependent Claim
142 words
A semiconductor integrated circuit device having a test circuit comprising: a plurality of gate cells arranged in a matrix; wiring means for connecting the gate cells so as to constitute a logic circuit; a plurality of row selection wires provided along said gate cells in a row direction, each of said gate cells being operatively connected to said row selection wire; a plurality of column read-out wires provided along said gate cells in a column direction, outputs of each of said gate cells being operatively connected to column read-out wires; row selection means, operatively connected to said row selection wires, for selecting any of said row selection wires and for selecting any of said gate cells connected to said selected row selection wire, and output means for reading out said gate cells arranged in said logic circuit through a column read-out wire.
Claim 3
Dependent Claim
35 words
A semiconductor integrated circuit device as claimed in claim 1, further comprising switching means, each means connected between a row selection wire and gate cell, said means being turned ON/OFF by said row selection means.
Claim 4
Dependent Claim
26 words
A semiconductor integrated circuit device as claimed in claim 1, wherein said row selection means comprises a ring counter constituted by a plurality of flip-flop circuits.
Claim 5
Dependent Claim
23 words
A semiconductor integrated circuit device as claimed in claim 1, wherein said output means comprises a column selection means and a data selector.
Claim 6
Dependent Claim
18 words
A semiconductor integrated circuit device as claimed in claim 1, wherein said output means comprises a shift register.
Claim 7
Dependent Claim
25 words
A semiconductor integrated circuit device as claimed 2, wherein said switching means is further connected between each said row selection wire and column read-out wire.
Claim 8
Dependent Claim
26 words
A semiconductcr integrated circuit device as claimed in claim 4, wherein said column selection means comprises a ring counter constituted by a plurality of flip-flop circuits.
Claim 9
Dependent Claim
22 words
A semiconductor integrated circuit device as claimed in claim 2, wherein said switching means comprises an n-p-n type transistor and a resistor.
Claim 10
Dependent Claim
26 words
A semiconductor integrated circuit device as claimed in claim 8, wherein said resistor is formed by extending a base diffusion area of said n-p-n type transistor.
Claim 11
Dependent Claim
19 words
A semiconductor integrated circuit device as claimed in claim 2, wherein said switching means comprises an MOS type transistor.
Claim 12
Dependent Claim
33 words
A semiconductor integrated circuit device as claimed in claim 1, wherein said logic circuit is divided into at least four blocks, each block provided with said row selection means and said output means.
References Cited (Backward Citations)
EP0073946A2
Cited
EP0118704A1
Cited
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.