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EP0147598A1
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Clocked differential cascode voltage switch logic circuit
Assignee: International Business Machines Corp
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Filing: 1984-11-14
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Granted: —
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Expires: 2004-11-14
Abstract
Abstract A clocked differential cascode voltage switch (CVS) logic system is provided for a complete logic family which has a first switching circuit (10) that produces a given output signal at a first output node (14) and a second switching circuit (12) that produces a second output signal which is the complement of that of the given output signal at a second output node (18). First and second clocked devices (24, 28) are connected from the first and second output nodes (14, 18), respectively, to a voltage source (V H ), the first and second inverters (32,34) are connected to the first and second output nodes (14, 18), respectively. Additionally, a regenerative circuit (26, 30) may be connected between the first and second output nodes (14, 18) and the voltage source (V H ).
Inventors
- 👤 William Robert Griffin
- 👤 Lawrence Griffith Heller
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 20:04
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1738
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
145 words
Clocked differential cascode voltage switch logic system, characterized by a first switching circuit (10) including input terminals (INPUTS) and a first output terminal (14) having a given signal, a second switching circuit (12) including input terminals (COMPLEMENTARY INPUTS) and a second output terminal (18) having a signal complementary to that of said first output terminal (14), a voltage source (V H ), a first clocked device (24) connected between said voltage source (V H ) and said first output terminal (14) a second clocked device (28) connected between said voltage source (V H ) and said second output terminal (18), a first inverter circuit (32) connected to said first output terminal (14), a second inverter circuit (34) connected to said second output terminal (18), and means for applying logic signals simultaneously to the input terminals of said first and second switching circuits (10 and 12).
Claim 2
Dependent Claim
145 words
Clocked differential cascode voltage switch logic system, characterized by a first switching circuit (10) including input terminals (INPUTS) and a first output terminal (14) having a given signal, a second switching circuit (12) including input terminals (COMPLEMENTARY INPUTS) and a second output terminal (18) having a signal complementary to that of said first output terminal (14), a voltage source (V H ), a first clocked device (24) connected between said voltage source (V H ) and said first output terminal (14) a second clocked device (28) connected between said voltage source (V H ) and said second output terminal (18), a first inverter circuit (32) connected to said first output terminal (14), a second inverter circuit (34) connected to said second output terminal (18), and means for applying logic signals simultaneously to the input terminals of said first and second switching circuits (10 and 12).
Claim 3
Dependent Claim
58 words
Logic system as set forth in claim 1 characterized by including clocked enabling means (16, 20) connected between each of said first and second switching circuits (10, 12) and a point of .-reference potential and means for simultaneously applying clocked pulses to said first and second clocked devices (24, 28) and to said clocked enabling means (16, 20).
Claim 4
Dependent Claim
32 words
Logic system as set forth in claim 1 or 2 characterized by including feedback circuits (26, 30) connected between said first and second output terminals (14, 18) and said voltage source (VH).
Claim 5
Dependent Claim
74 words
Logic system as set forth in claim 3 characterized by including a first P or N channel feedback transistor (26) connected in parallel with said first clocked device (24) having a control gate connected to the output of said first inverter (32) and a second P or N channel feedback transistor (30) connected in parallel with said second clocked device (28) having a control gate connected to the output of said second inverter (34).
Claim 6
Dependent Claim
120 words
Logic system as set forth in claims 1 to 4, characterized in that said first inverter circuit (32) includes a first P channel transistor (32A) and a first N channel transistor (32B) serially interconnected between said voltage source (V H ) and a point of reference potential with the control gates of each of said transistors being connected to said first output terminal (14), and said second inverter circuit (34) includes a second P channel transistor (34A) and a second N channel transistor (34B) serially interconnected between said voltage source (V H ) and said point of reference potential with the control gates of each of said second P and N transistors being connected to said second output terminal (18).
Claim 7
Dependent Claim
44 words
Logic system as set forth in claims 1 to 5, characterized in that said clocked devices (24, 28) are either P channel or N channel devices and that means are included for applying clocked pulses (C) simultaneously to the control gates of said devices.
Claim 8
Dependent Claim
40 words
Logic system as set forth in claims 1 to 6, characterized in that each of said first and second clocked devices (24, 28) includes a P channel transistor and said clocked enabling means (16, 20) includes an N channel transistor.
Claim 9
Dependent Claim
35 words
Logic system as set forth in claims 1 to 6, characterized in that each of said first and second clocked devices (24, 28) and said clocked enabling means (16, 20) includes an N channel transistor.
Claim 10
Dependent Claim
31 words
Logic system as set forth in claims 1 to 8, characterized in that said first and second switching circuits (10, 20) are arranged in the form of an exclusive OR circuit.
References Cited (Backward Citations)
US4367420A
Cited
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