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EP0125943A1
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An indium phosphide-boron phosphide heterojunction bipolar transistor
Assignee: Honeywell International Inc
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Filing: 1984-04-05
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Granted: —
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Expires: 2004-04-05
Abstract
Abstract A heterojunction bipolar transistor having an n-type epitaxial indium phosphide collector layer (16) grown on a semi-insulating indium phosphide substrate (18) with an n+ buried layer (20), a p-type indium phosphide base (26) and an epitaxpial, n-type boron phosphide wide gap emitter (24). The p- type base region (26) is formed by ion implantation of magnesium ions into the collector layer (16). The transistor is applicable to millimeter wave applications due to the high electron mobility in the indium phosphide base. The wide gaps of both the boron phosphide (2.2eV) and indium phosphide (1.34eV) permit operation up to 350°C. The transistor is easily processed using metal organic-chemical vapor deposition (MO-CVD) and standard microelectronic techniques.
Inventors
- 👤 Krishna Prasad Pande
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 02:00
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10D10/80; H10D10/821; H10D62/00; H10D62/80; H10D62/82; H10D62/824
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
67 words
An improved indium phosphide bipolar transistor having an n- type epitaxial indium phosphide collector layer (16) disposed on a semi-insulating indium phosphide substrate (18) and a p- type indium phosphide base region (26) formed in said collector layer (16), the improvement characterized by an epitaxial n- type boron phosphide emitter (24) disposed on the surface of said p- type base region (26) and forming a heterojunction therewith.
Claim 2
Dependent Claim
67 words
An improved indium phosphide bipolar transistor having an n- type epitaxial indium phosphide collector layer (16) disposed on a semi-insulating indium phosphide substrate (18) and a p- type indium phosphide base region (26) formed in said collector layer (16), the improvement characterized by an epitaxial n- type boron phosphide emitter (24) disposed on the surface of said p- type base region (26) and forming a heterojunction therewith.
Claim 3
Dependent Claim
24 words
The improvement of Claim 1 further including a buried n+ indium phosphide layer (20) disposed between said collector layer (16) and said substrate (18).
Claim 4
Dependent Claim
47 words
The improvement of Claim 2 further including: an n+ indium phosphide collector contact region (12) disposed in said collector layer; a p+ indium phoshide base contact region (14) disposed in said base region (26); and and n+ boron phosphide emitter contact region (22) disposed on said emitter.
Claim 5
Dependent Claim
77 words
The improvement of Claim 3 further including: an insulator layer (28) disposed on the surface of the transistor, said insulator layer having openings exposing said collector, base and emitter contact regions (12, 14, 22); and at least three metallic electrodes (30, 32, 34) disposed on the surface of insulator layer and electrically isolated from each other, each of said electrodes contacting one of said exposed collector, base and emitter contact regions (12, 14, 22) through said openings.
Claim 6
Independent Claim
138 words
A method for forming a bipolar heterojunction indium phosphide transistor characterized by the steps of: epitaxially growing a buried n+ indium phosphide layer (20) on a selectively etched semi-insulating indium phosphide substrate (18); epitaxially growing an n- type indium phosphide collector layer (16) over said buried n+ layer (20); implanting silicon ions into said collector layer (16) to form an n+ collector contact region (12) about the perimeter of said collector layer (16); implanting metal ions into the central region of said collector layer (16) to form a p- type base region (26) and a p+ base contact region (14); epitaxially growing an n- type boron phosphide layer over said base region (26) to form an emitter (24); and epitaxially growing an n+ type boron phosphide layer over said emitter (24) to form an emitter contact region (22).
Claim 7
Independent Claim
138 words
A method for forming a bipolar heterojunction indium phosphide transistor characterized by the steps of: epitaxially growing a buried n+ indium phosphide layer (20) on a selectively etched semi-insulating indium phosphide substrate (18); epitaxially growing an n- type indium phosphide collector layer (16) over said buried n+ layer (20); implanting silicon ions into said collector layer (16) to form an n+ collector contact region (12) about the perimeter of said collector layer (16); implanting metal ions into the central region of said collector layer (16) to form a p- type base region (26) and a p+ base contact region (14); epitaxially growing an n- type boron phosphide layer over said base region (26) to form an emitter (24); and epitaxially growing an n+ type boron phosphide layer over said emitter (24) to form an emitter contact region (22).
Claim 8
Dependent Claim
70 words
The method of Claim 5 wherein said steps of growing said n- type and n+ type boron phosphide layers includes the steps of: depositing an insulating layer (28) over said collector layer; etching an opening (52) in said insulator layer exposing a portion of said base region (26); and epitaxially growing said n- type boron phosphide and n+ boron phosphide layers over said exposed portion of said base region (26).
Claim 9
Dependent Claim
80 words
The method of Claim 6 further including the steps of: etching openings in said insulating layer to expose said collector and base contact regions (12, 14); and depositing individual metallic electrodes (30, 32, 34) on the surface of said insulating layer and said collector, base, and emitter contact regions (12, 14, 22), said electrodes (30, 32, 34) electrically isolated from one another and each electrode making electrical contact with a different one of said collector, base and emitter contact regions.
Claim 10
Dependent Claim
45 words
The method of Claim 7 wherein said step of depositing electrodes comprises the steps of: thermal evaporating individual gold-germanium-nickel alloy electrodes (30, 34) on said collector and emitter contact regions (12, 22); and evaporating a gold-zinc-platinum alloy electrode (32) on said base contact regions (14).
Claim 11
Dependent Claim
42 words
The method of Claim 5 wherein said step of growing a buried n+ layer (20) grows said buried n+ layer to a thickness between 1 to 2 micrometers having a carrier concentration of approximately 2 to 5 x 1018 cm -3 .
Claim 12
Dependent Claim
54 words
The method of Claim 9 wherein said step of growing a buried n+ layer (20) includes the step of chemical vapor depositing said buried n+ layer by reacting phosphine with trietylindium and using sulfer chloride as the dopant source to adjust the carrier concentration to approximately 2 to 5 x 10 18 cm .
Claim 13
Dependent Claim
44 words
The method of Claim 5 wherein said step of growing an n- type collector layer (16) grows said n- type collector layer to a thickness between 0.5 and 1.0 micrometers and having a carrier concentration of approximately 2 x 10 15 cm 3 .
Claim 14
Dependent Claim
48 words
The method of Claim 11 wherein said step of growing an n- type collector layer (16) includes the step of chemical vapor depositing said n- type collector layer by reacting phosphine with triethylindium and using sulfer chloride to adjust the carrier concentration to 2 x 10 15 cm-3.
Claim 15
Dependent Claim
79 words
The method of Claim 5 wherein said step of implanting silicon ions to form an n+ collector contact region (12) comprises the steps of: depositing an insulating layer (38) on the surface of said collector layer (16); etching said insulating layer to expose a surface area defining said collector contact region (12); and implanting silicon ions in said exposed surface to form said collector contact region having a carrier concentration of approximately 2 x 10 18 cm -3 .
Claim 16
Dependent Claim
157 words
The method of Claim 5 wherein said step of implanting metal ions to form a p- type base region and a p+ base contact region comprises the steps of: depositing an insulating layer (44) on the surface of collector layer (16); etching said insulating layer to expose a surface area of said collector layer defining said base contact region (14); implanting said base region (26) and said base contact region (14) with metal ions having sufficient energy to penetrate said insulator layer (44) to form said p- type base region (26) in said collector layer underlying said insulator region having a carrier concentration of approximately 6 to 8 x10 17 cm -3 ; and reducing the energy of said implanting ions to a level insufficient to penetrate said insulating layer (44) to form said base contact region (14) having a carrier concentration of greater than 10 18 cm -3 in the exposed portion of said collector layer.
Claim 17
Dependent Claim
18 words
The method of Claim 14 wherein said metal ions are selected from a group comprising magnesium and beryllium.
Claim 18
Dependent Claim
35 words
The method of Claim 5 further including the step of electrically isolating said transistor by implanting boron ions in the area surrounding said collector, base and emitter regions (16, 26, 24) to render it nonconductive.
Claim 19
Dependent Claim
42 words
The method of Claim 5 further including the step of electrically isolating said transistor by etching away the portion of the collector layer (16) and buried n+ layer (20) surrounding said collector, base and emitter regions to produce a mesa type structure.
References Cited (Backward Citations)
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