Patent EP0102802A1 successfully refreshed from Google Patents.
EP0102802A1
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Photolithographic process for fabricating thin film transistors
Assignee: Xerox Corp
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Filing: 1983-08-23
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Granted: —
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Expires: 2003-08-23
Abstract
Abstract A photolithographic method for fabricating thin film transistors and thin film transistor arrays in which the contamination vulnerable semi-conductor-insulator interfaces are formed in a single vacuum pump-down operation. To minimize step coverage problems, quasi-planar construction is employed to provide a planar substructure for receipt of the deposited thin semiconductor layer.
Inventors
- 👤 Michael Poleshuk
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 11:33
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/01; H10D86/021; H10D86/0231; H10D30/00; H10D30/60; H10D30/67; H10D30/674; H10D30/675; H10D86/40; H10D86/60; Y; Y10; Y10S; Y10S438/00; Y10S438/913
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
41 words
A method of forming an active region of a thin film transistor characterised by selectively depositing thin film layers of an insulator, a semi- conductor and an insulator upon the surface portions of a substrate in successive sequence under continuous vacuum.
Claim 2
Independent Claim
41 words
A method of forming an active region of a thin film transistor characterised by selectively depositing thin film layers of an insulator, a semi- conductor and an insulator upon the surface portions of a substrate in successive sequence under continuous vacuum.
Claim 3
Dependent Claim
24 words
The method of claim 1, wherein said surface portions of the substrate are exposed by a predetermined pattern of openings in a photoresist mask.
Claim 4
Dependent Claim
40 words
The method of claim 1 or claim 2 wherein the surface portions of said substrate comprise substantially planar surface portions of a composite layer, said composite layer including at least one conductive film pattern surrounded by an insulative film pattern.
Claim 5
Dependent Claim
19 words
The method of claim 3, wherein said substrate includes at least one other conductive layer underlying said composite layer.
Claim 6
Independent Claim
241 words
A method of forming a thin film transistor, comprising the steps of: a) forming a first composite layer on a surface of a substrate, said first composite layer having a first substantially planar surface and including a conductive film pattern defining at least one gate electrode surrounded by an insulative film pattern; b) depositing a gate insulator layer on the planar surface of said first composite layer; c) forming a second composite layer on said deposited insulator layer, said second composite layer having a second substantially planar surface and including at least one conductive film pattern surrounded by an insulative film pattern, said conductive film pattern defining at least source and drain electrodes; d) forming on said second planar surface a masking layer having a predetermined pattern of openings therein exposing portions of said source and drain electrodes and said deposited insulator layer; e) sequentially depositing, under continuous vacuum, a third insulator layer, a semiconductor layer, and a fourth insulator layer on said masking layer and on the exposed portions of said deposited insulator layer; f) removing said masking layers and the portions of the third insulator layer, the semiconductor layer, and the fourth insulator layer deposited thereon; g) selectively removing portions of said fourth insulator to define the transistor channel length and expose selected portions of said semi- conductor layers; and h) selectively forming conductive contacts between the source and drain electrodes and said selected portions of said semiconductor layer.
Claim 7
Independent Claim
241 words
A method of forming a thin film transistor, comprising the steps of: a) forming a first composite layer on a surface of a substrate, said first composite layer having a first substantially planar surface and including a conductive film pattern defining at least one gate electrode surrounded by an insulative film pattern; b) depositing a gate insulator layer on the planar surface of said first composite layer; c) forming a second composite layer on said deposited insulator layer, said second composite layer having a second substantially planar surface and including at least one conductive film pattern surrounded by an insulative film pattern, said conductive film pattern defining at least source and drain electrodes; d) forming on said second planar surface a masking layer having a predetermined pattern of openings therein exposing portions of said source and drain electrodes and said deposited insulator layer; e) sequentially depositing, under continuous vacuum, a third insulator layer, a semiconductor layer, and a fourth insulator layer on said masking layer and on the exposed portions of said deposited insulator layer; f) removing said masking layers and the portions of the third insulator layer, the semiconductor layer, and the fourth insulator layer deposited thereon; g) selectively removing portions of said fourth insulator to define the transistor channel length and expose selected portions of said semi- conductor layers; and h) selectively forming conductive contacts between the source and drain electrodes and said selected portions of said semiconductor layer.
Claim 8
Dependent Claim
75 words
The method of claim 5 wherein step (a) comprises: al) forming a gate electrode of a given thickness of conductive material on a portion of a surface of a substrate; and a2) forming a first insulator layer on selected remaining portions of the surface of said substrate not occupied by the gate electrode, said insulating layer having a thickness substantially equal to the thickness of said gate electrode to thereby form the first planar surface.
Claim 9
Dependent Claim
83 words
The method of claim 5 or claim 6 wherein step (c) comprises: cl) forming source and drain electrodes of given equal thickness of a conductive material on selected portions of said gate insulator layer; and c2) forming a second insulator layer on selected remaining portions of the gate insulator layer not occupied by said source and drain electrodes, said second insulator layer having a thickness substantially equal to the thickness of said source and drain electrodes to thereby form the second planar surface.
Claim 10
Independent Claim
26 words
The method of any one of claims 5 to 7, wherein said step (g) comprises selectively removing portions of said fourth insulator layer by dry etching.
Claim 11
Dependent Claim
12 words
The method of claim 8, wherein said dry etching comprises plasma etching.
Claim 12
Independent Claim
67 words
The method of any one of claims 5 to 7, wherein said step (g) comprises: (gl) forming on said fourth insulator layer a photoresist masking layer having a predetermined pattern of openings therein exposing portions of said fourth insulator; (g2) plasma etching the exposed portions of said fourth insulator layer to expose selected portions of said semiconductor layer; and (g3) removing said masking layer by plasma etching.
References Cited (Backward Citations)
US4035276A
Cited
GB2077039A
Cited
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