Patent EP0100529A1 successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0100529A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

High speed field-effect transistor employing heterojunction

Assignee: NEC Corp
•
Filing: 1983-07-28
•
Granted: —
•
Expires: 2003-07-28
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A high speed FET having a heterojunction is disclosed. The FET is operable with a small dynamic or internal resistance and a high applied voltage and comprises at least three semiconductor layers so that the depletion layer formed into the second semi-conductor layer (23) by the third semiconductor layer (24) functioning as a gate electrode extends over the total thickness or a part of the second semiconductor layer (23) when said gate electrode is not biased and changes its thickness when said gate electrode is biased.

Inventors

  • 👤 Keiichi Ohata

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-28 15:23
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/343; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/473; H10D30/4732; H10D30/475; H10D30/4755; H10D30/80; H10D64/00; H10D64/60; H10D64/602

Claims Analysis

Total Claims: 22
Claim 1
Independent Claim 125 words
A field-effect transistor comprising: a first semiconductor layer which is intrinsic or, of a first conductivity type having a low impurity density; a second semiconductor layer of a second conductivity type formed on said first semiconductor layer, said second semiconductor layer inducing an inversion region of said second conductivity type at the interface with said first semiconductor layer as a result of the contact therebetween; a third semiconductor layer of said first conductivity type formed on said second semiconductor layer and forming a depletion layer in said second semiconductor layer over the total thickness of second semiconductor layer; means for functioning said third semiconductor layer as a gate electrode; and a drain electrode and a source electrode separately and electrically connected to said inversion region.
Claim 2
Dependent Claim 125 words
A field-effect transistor comprising: a first semiconductor layer which is intrinsic or, of a first conductivity type having a low impurity density; a second semiconductor layer of a second conductivity type formed on said first semiconductor layer, said second semiconductor layer inducing an inversion region of said second conductivity type at the interface with said first semiconductor layer as a result of the contact therebetween; a third semiconductor layer of said first conductivity type formed on said second semiconductor layer and forming a depletion layer in said second semiconductor layer over the total thickness of second semiconductor layer; means for functioning said third semiconductor layer as a gate electrode; and a drain electrode and a source electrode separately and electrically connected to said inversion region.
Claim 3
Dependent Claim 31 words
The field-effect transistor as claimed in Claim 1, wherein said field-effect transistor further comprises regions of said second conductivity type formed between said inversion region and said source and drain electrodes.
Claim 4
Dependent Claim 28 words
The field-effect transistor as claimed in Claim 1, wherein the impurity density of said third semiconductor layer is higher than the impurity density of said second semiconductor layer.
Claim 5
Dependent Claim 29 words
The field-effect transistor as claimed in Claim 3, wherein the impurity contained in said third semiconductor layer is diffused into said second semiconductor layer from said third semiconductor layer.
Claim 6
Dependent Claim 35 words
The field-effect transistor as claimed in Claim 1, wherein said first conductivity type is p-type, and said second semiconductor layer is of a semiconductor which has a lower electron affinity than said first semiconductor layer.
Claim 7
Dependent Claim 26 words
The field-effect transistor as claimed in Claim 5, wherein said first semiconductor layer is of GaAs, and said second and third semiconductor layers are of GaAℓAs.
Claim 8
Dependent Claim 26 words
The field-effect transistor as claimed in Claim 5, wherein said first and third semiconductor layers are of GaAs, and said second semiconductor layer is of GaAQAs.
Claim 9
Dependent Claim 41 words
The field-effect transistor as claimed in Claim 1, wherein said first conductivity type is n-type, and said second semiconductor layer is of a semiconductor which has a larger sum of electron affinity and energy band gap than said first semiconductor layer.
Claim 10
Dependent Claim 26 words
The field-effect transistor as claimed in Claim 8, wherein said first semiconductor layer is of Ge, and said second and third semiconductor layers are of GaAs.
Claim 11
Dependent Claim 43 words
The field-effect transistor as claimed in Claim 1, wherein said first semiconductor layer is a layer selected from a group consisting of GaAs and InGaAs, and said second and third semiconductor layers are layers selected from a group of GaAℓAs, InP and AℓInAs.
Claim 12
Dependent Claim 27 words
The field-effect transistor as claimed in Claim 1, wherein said depletion'layer extends over the total thickness of said second semiconductor layer when said gate electrode is unbiased.
Claim 13
Dependent Claim 47 words
The field-effect transistor as claimed in Claim 1, wherein said depletion layer does not extend over the total thickness of said second semiconductor layer when said gate electrode is unbiased but extends over the total thickness of said second semiconductor layer when said gate electrode is biased.
Claim 14
Dependent Claim 50 words
The field-effect transistor as claimed in Claim 1 further comprising a fourth semiconductor layer of second on second said conductivity type formed said semiconductor layer and forming a barrier preventing second oxidation and deterioration of said semi- conductor layer while maintaining a low surface second potential of said semiconductor layer.
Claim 15
Dependent Claim 35 words
The field-effect transistor as claimed in Claim 13, wherein said first conductivity type is p-type, and said second semiconductor layer is of a semiconductor which has a lower electron affinity than said first semiconductor layer.
Claim 16
Dependent Claim 29 words
The field-effect transistor as claimed in Claim 14, wherein said first and fourth semiconductor layers are of GaAs, and said second and third semi- conductor layers are of GaAℓAs.
Claim 17
Dependent Claim 26 words
The field-effect transistor as claimed in third Claim 14, wherein said 'first/and fourth semiconductor layers are of GaAs, and said secbnd semiconductor layer is of GaAYAs.
Claim 18
Dependent Claim 42 words
The field-effect transistor -as claimed in Claim 13, wherein said first conductivity type is n-type, and said second semiconductor layer is of a semiconductor which has a larger sum of electron affinity and energy band gap than said first semi- conductor layer.
Claim 19
Dependent Claim 26 words
The field-effect transistor as claimed in Claim 17, wherein said first semiconductor layer is of Ge, and said second and fourth semiconductor layers are of GaAs.
Claim 20
Dependent Claim 45 words
The field-effect transistor as claimed in Claim 13, wherein said first semiconductor layer is a layer selected from a group consisting of GaAs and InGaAs, and said second and third semi- conductor layers are layers selected from a group of GaAℓ As, InP and AℓInAs.
Claim 21
Dependent Claim 28 words
The field-effect transistor as claimed in Claim 13, wherein said depletion layer extends over the total thickness of said second semiconductor layer when said gate electrode is unbiased.
Claim 22
Dependent Claim 46 words
The field-effect transistor as claimed in Claim 13, wherein said-depletion layer does not extend over the total thickness of said second semiconductor layer when said gate electrode is unbiased but extends over the total thickness of said second semiconductor layer when said gate electrode is biased.

References Cited (Backward Citations)

FR2386903A1 Cited
DE2913068A1 Cited
EP0064370A2 Cited

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag