Digital player for reproducing a digital signal sequence

Claim 2

A pulse width detector comprising: a first pulse width detector (29) for detecting a high-level pulse width of a digital signal sequence including an information signal and a synchronizing signal of a specific pattern reproduced from a recording medium; a second pulse width detector (30) for detecting a low-level pulse width of said digital signal sequence; and an arithmetic operation circuit (37) connected to output terminals of said first and second detectors for producing an original digital pulse width data in accordance with the output data of said first and second detectors.

Claim 3

A pulse width detector according to Claim 1 wherein said arithmetic operation circuit is one of an adder, a subtractor and an averaging circuit.

Claim 4

A pulse width detector according to Claim 1 wherein said first and second pulse width detectors each detects a pulse width of from a rise to the next rise or from a fall to the next fall of synchronizing signal pulse.

Claim 5

A pulse width detector according to Claim 1 wherein said first pulse width detector detects a high-level pulse width of said synchronizing signal and said second pulse width detector detects a low-level pulse width of said synchronizing signal.

Claim 6

A pulse width detector according to Claim 1 wherein said first pulse width detector detects a maximum or minimum high-level pulse width of said digital signal sequence and said second pulse width detector detects a maximum or minimum low-level pulse width of said digital signal sequence.

Claim 7

A digital player which utilizes the pulse width detector according to Claim 4 wherein said arithmetic operation circuit is an adder or an averaging circuit and an output of said arithmetic operation circuit is supplied to a motor (2) through a motor drive circuit (52) to control a rotational speed of said motor.

Claim 8

A digital player which utilizes the pulses width detector according to Claim 5 wherein said arithmetic operation circuit is an adder or an averaging circuit and an output of said arithmetic operation circuit is supplied to a motor (2) through a motor drive circuit (52) to control a rotational speed of said motor.

Claim 9

A digital player which utilizes the pulse width detector according to Claim 1 wherein said arithmetic operation circuit is a subtractor, an output of said subtractor is supplied to a digital-to-analog converter (64), an output of said converter is supplied to a voltage comparator (.59) as a comparison voltage, and an output of said voltage comparator is used to control a slicing level for said digital signal sequence to equalize the high-level pulse width and the low-level pulse width of said digital signal sequence.

Claim 10

A digital player which utilizes the pulse width detector according to Claim 4 wherein said arithmetic operation circuit includes an adder or an averaging circuti (37) and a subtractor (63), an output of said adder or said averaging circuit is supplied to a motor (]) through a motor drive circuit (52) to control a rotational speed of said motor, an output of said subtractor is supplied to a digital-to-analog converter (64), an output of said converter is supplied to a voltage comparator (59) as a comparison voltage, and an output of said comparator is used to equalize the high-level pulse width and the low-level pulse width of said digital signal sequence.

Claim 11

A digital player which utilizes the pulse width detector according to Claim 5 wherein said arithmetic operation circuit includes an adder or an averaging circuit (37) and a subtracter (63), an output of said adder or said averaging circuit is supplied to a motor (2) through a motor drive circuit (52) to control a rotational speed of said motor, an output of said subtractor is supplied to a digital-to-analog converter (64), an output of said converter is supplied to a voltage comparator (59) as a comparison voltage, and an output of said comparator is used to equalize the high-level pulse width and the low-level pulse width of said digital signal sequence.

Claim 12

A digital player having a comparator (59) for comparing an input signal of a digital signal sequence reproduced from a recording medium (1) with a predetermined reference voltage and a signal processing circuit (101) for processing an output signal of said comparator to reproduce an original signal, comprising: a switch (114); a fixed voltage generator (97) connected to said switch; at least one voltage generator connected to said switch, including a high-level pulse width detector (95) for detecting a pulse width in a high-level range in which the input signal to said comparator is larger than said predetermined reference voltage, a low-level pulse width detector (95) for detecting a pulse width in a low-level range in which the input signal to said comparator is smaller than said predetermined reference voltage and an arithmetic operation circuit (91) for calculating a difference between the output of said high-level pulse width detector and the output of said low-level pulse width detector; and an operation status discriminator (112) for discriminating an operation status of said digital player; the output of said switch being applied to a reference terminal of said comparator, said switch being controlled by the output of said operation status discriminator to switch said predetermined reference voltage of said comparator.

Claim 13

A digital player having a comparator (59) for comparing an input signal of a digital signal sequence reproduced from a recording medium (1) with a predetermined reference voltage and a signal processing circuit (101) for processing an output signal of said comparator to reproduce an original signal, comprising: a switch (114); a fixed voltage generator (97) connected to said switch; at least one voltage generator connected to said switch, including a high-level pulse width detector (95) for detecting a pulse width in a high-level range in which the input signal to said comparator is larger than said predetermined reference voltage, a low-level pulse width detector (95) for detecting a pulse width in a low-level range in which the input signal to said comparator is smaller than said predetermined reference voltage and an arithmetic operation circuit (91) for calculating a difference between the output of said high-level pulse width detector and the output of said low-level pulse width detector; and an operation status discriminator (112) for discriminating an operation status of said digital player; the output of said switch being applied to a reference terminal of said comparator, said switch being controlled by the output of said operation status discriminator to switch said predetermined reference voltage of said comparator.

Claim 14

A digital player according to Claim 11 wherein said high-level pulse width detector and said low-level pulse width detector each detects a maximum or minimum pulse width within a predetermined time period.

Claim 15

A digital player according to Claim 11 further comprising a voltage hold circuit (119) for holding said reference voltage of said comparator by said operation status discriminator.

Claim 16

A digital player according to Claim 11 wherein said operation status discriminator discriminates whether a maximum or minimum pulse width within a predetermined time period is within a predetermined width or not and connects said switch to said fixed voltage generator if above said predetermined width and connects said switch to said voltage generator if within said predetermined width.

Claim 17

A digital player according to Claim 11 wherein said voltage hold circuit is controlled by an output signal of an input signal (281 magnitude detector C121).

Claim 18

A digital player according to Claim 11 wherein said fixed voltage generator and said switch include a first latch (186), a comparator (36) which receives an input signal (194) to said first latch and an output signal from said first latch, a first clock line (196) connected to said first latch and controlled by said comparator, a second latch (174) which receives the output signal of said first latch and a switch (193) for alternatively selecting second and third latch clock lines (191, 192) to connect the selected clock line to said second latch, the control of said switch and the connection and disconnection of the output of said comparator (36) being simultaneously effected.