Patent US3507748A successfully refreshed from Google Patents.
Patent EP0063916A1 successfully refreshed from Google Patents.
EP0063916A1
Expired / Lapsed
EP
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Semiconductor intregrated circuits and manufacturing process thereof
Assignee: NTT Inc
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Filing: 1982-04-21
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Granted: —
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Expires: 2002-04-21
Abstract
Abstract A semiconductor integrated circuit in which layers such as a field isolation region (2), a gate electrode (4), interlayer insulating films (9, 11, 13, 15) and interconnection lines (10, 12, 14) are formed by the combined use of a lift-off process and an ECR plasma deposition process. According to the present invention, even if vertical dimensions of patterns of the respective layers are large as compared with their lateral dimensions, the upper surfaces of the respective layers can be planarized, permitting the fabrication of an LSI of high packing density, high operating speed and high reliability which is free from shorting and breakage of the interconnection lines.
Inventors
- 👤 Manabu Itsumi
- 👤 Kohei Ehara
- 👤 Susumu Muramoto
- 👤 Seitaro Matsuo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 01:42
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/058; H10P; H10P76/00; H10P76/20; H10P76/202; H10W10/00; H10W10/01; H10W10/011; H10W10/10; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/951
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
91 words
A semiconductor integrated circuit comprising: a first conductor layer formed as an electrode to extend in contact with an active region in a semiconductor substrate directly or indirectly through an insulating layer; a first insulating layer formed adjacent said first conductor layer to extend flush therewith; a second conductor layer formed as an interconnection line to extend on said first conductor layer and said first insulating layer, and connected with at least said first conductor layer; and a second insulating layer formed adjacent said second conductor layer to extend flush therewith.
Claim 2
Dependent Claim
91 words
A semiconductor integrated circuit comprising: a first conductor layer formed as an electrode to extend in contact with an active region in a semiconductor substrate directly or indirectly through an insulating layer; a first insulating layer formed adjacent said first conductor layer to extend flush therewith; a second conductor layer formed as an interconnection line to extend on said first conductor layer and said first insulating layer, and connected with at least said first conductor layer; and a second insulating layer formed adjacent said second conductor layer to extend flush therewith.
Claim 3
Dependent Claim
162 words
A semiconductor integrated circuit according to claim 1 wherein said active region is composed of a source region, a channel region and a drain region; wherein a field isolation region formed of an insulating material is provided in said semiconductor substrate for isolating said active region from other active regions, the upper surface of said field isolation region being substantially flush with the upper surface of said semiconductor substrate, said first conductor layer being composed of a gate electrode, a source electrode and a drain electrode, said gate electrode being formed to extend over said channel region through said insu- laing layer formed therebetween, and said source drain electrodes being provided in contact with said source drain regions, respectively; and wherein said second conductor layer is composed of a source electrode interconnection line, a gate electrode interconnection line and a drain electrode interconnection line, said source, gate and drain electrode interconnection lines being connected to said source, gate and drain electrodes, respectively.
Claim 4
Dependent Claim
28 words
A semiconductor integrated circuit according to claim 1 wherein at least two said active regions are provided and MOS FETs formed in said individual active regions are complementary.
Claim 5
Dependent Claim
170 words
A semiconductor integrated circuit according to claim 1 wherein said active region is composed of an emitter region, a base region and a collector region; wherein a rectangular-sectioned isolation portion of an insulating material is provided between said emitter and collector regions for isolating them from each other; wherein a filed isolation region of an insulating material is provided in said semiconductor substrate for isolating said active region from other active regions, the upper surface of said isolation region being substantially flush with the upper surface of said semiconductor substrate; wherein said first conductor layer is composed of an emitter electrode, a base electrode and a collector electrode, said emitter, base and collector electrodes being provided in contact with said emitter, base and collector regions, respectively; and wherein said second conductor layer is composed of an emitter electrode interconnection line, a base electrode interconnection line and a collector electrode interconnection line, said emitter , base and collector electrode interconnection lines being connected to said emitter, base and collector electrodes, respectively.
Claim 6
Dependent Claim
33 words
A semiconductor integrated circuit according to claims 2 and 4 wherein said field isolation region, said emitter, base and collector electrodes and said first and second insulating layers are rectangular in cross section.
Claim 7
Independent Claim
112 words
A method for the manufacture of a semiconductor integrated circuit, comprising the steps of: forming a resist pattern on a semiconductor substrate or a first material layer composed of plural layers formed on said semiconductor substrate; removing a portion of said first material layer through using said resist pattern as a mask to form a recess in said first material layer; forming a second material layer by a plasma deposition process to thickness substantially equal to the depth of said recess; and removing said second material layer on said resist pattern by a lift-off process, along with said resist pattern; wherein said steps are each carried out repeatedly at least four times.
Claim 8
Independent Claim
112 words
A method for the manufacture of a semiconductor integrated circuit, comprising the steps of: forming a resist pattern on a semiconductor substrate or a first material layer composed of plural layers formed on said semiconductor substrate; removing a portion of said first material layer through using said resist pattern as a mask to form a recess in said first material layer; forming a second material layer by a plasma deposition process to thickness substantially equal to the depth of said recess; and removing said second material layer on said resist pattern by a lift-off process, along with said resist pattern; wherein said steps are each carried out repeatedly at least four times.
Claim 9
Independent Claim
402 words
A method for the manufacture of a semiconductor integraed circuit, comprising the steps of: forming a first resist pattern on a semiconductor substrate; removing a portion of said semiconductor substrate through using said first resist pattern as a mask to form a groove in said semiconductor substrate; filling up said groove with an insulating material by a plasma deposition process; removing said insulating material on said first resist pattern by a lift-off process, together with said first resist pattern; forming an insulating film on said semiconductor substrate; forming on said insulating film a first conductor layer which will ultimately serve as a gate electrode; forming a second resist pattern on said first conductor layer; removing a portion of said first conductor layer through using said second resist pattern as a mask to form a recess in said first conductor layer; forming a source region and a drain region in said semiconductor substrate through using said first conductor layer as a mask; filling up said recess of said first conductor layer with a first insulating layer by the plasma deposition process; removing said insulating layer on said second resist pattern by the lift-off process, together with said second resist pattern; forming a third resist pattern on said first conductor layer and said insulating layer; removing said insulating film and said first insulating layer on laid source and drain regions through using said third resist pattern as a majk to form recesses in said insulating film and said first insulating layer; filling said recesses of said insulating film and said first insulating layer, by the plasma deposition process, with another first conductor layer which is different from said first conductor layer and will form a source electrode and a drain electrode; removing said another first conductor layer on said third resist pattern by the lift-off process, together with said third resist pattern; forming a second conductor layer on said another first conductor layer and said first insulating layer; forming a fourth resist pattern on said second conductor layer; removing a portion of said second conductor layer through using said fourth resist pattern as a mask to form a recess in said second conductor layer; filling up said recess of said second conductor layer with a second insulating layer by the plasma deposition process; and removing said second insulating layer on said fourth resist pattern by the lift-off process, together with said fourth resist pattern.
Claim 10
Independent Claim
402 words
A method for the manufacture of a semiconductor integraed circuit, comprising the steps of: forming a first resist pattern on a semiconductor substrate; removing a portion of said semiconductor substrate through using said first resist pattern as a mask to form a groove in said semiconductor substrate; filling up said groove with an insulating material by a plasma deposition process; removing said insulating material on said first resist pattern by a lift-off process, together with said first resist pattern; forming an insulating film on said semiconductor substrate; forming on said insulating film a first conductor layer which will ultimately serve as a gate electrode; forming a second resist pattern on said first conductor layer; removing a portion of said first conductor layer through using said second resist pattern as a mask to form a recess in said first conductor layer; forming a source region and a drain region in said semiconductor substrate through using said first conductor layer as a mask; filling up said recess of said first conductor layer with a first insulating layer by the plasma deposition process; removing said insulating layer on said second resist pattern by the lift-off process, together with said second resist pattern; forming a third resist pattern on said first conductor layer and said insulating layer; removing said insulating film and said first insulating layer on laid source and drain regions through using said third resist pattern as a majk to form recesses in said insulating film and said first insulating layer; filling said recesses of said insulating film and said first insulating layer, by the plasma deposition process, with another first conductor layer which is different from said first conductor layer and will form a source electrode and a drain electrode; removing said another first conductor layer on said third resist pattern by the lift-off process, together with said third resist pattern; forming a second conductor layer on said another first conductor layer and said first insulating layer; forming a fourth resist pattern on said second conductor layer; removing a portion of said second conductor layer through using said fourth resist pattern as a mask to form a recess in said second conductor layer; filling up said recess of said second conductor layer with a second insulating layer by the plasma deposition process; and removing said second insulating layer on said fourth resist pattern by the lift-off process, together with said fourth resist pattern.
Claim 11
Independent Claim
27 words
A method for the manufacture of a semiconductor integrated circuit according to claims 6 and 7 wherein said plasma deposition process is an ECR plasma deposition process.
References Cited (Backward Citations)
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