EP0062431A1
Expired / Lapsed
EP
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A one chip microcomputer
Assignee: Fujitsu Ltd
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Filing: 1982-03-19
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Granted: —
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Expires: 2002-03-19
Abstract
Abstract A one ship microcomputer comprises: a central processing unit (CPU 1) having arithmetic, logic and control units; a random access memory (RAM 3) for storing intermediate data with instructions processed by the central processing unit (CPU 1); means (4, 23) for carrying first data processed by the central processing unit (CPU 1); a direct memory access controller (DMAC 2) controlled by the central processing unit (CPU 1) for providing a read out of second data stored in a predetermined area of the random access memory (RAM 3); means (9, 21) for carrying the second data stored in the predetermined area of the random access memory (RAM 3); terminal means (P) coupled to said means for carrying the first and second data to provide an output for the first data during a central processing unit operating mode and for the second data during a direct memory access operating mode; and, a time division means (5) controlled by the direct memory access controller (DMAC 2) for transmitting the first or the second data to the terminal means (P). This has the advantage that a direct transfer can take place between the RAM 3 and the outside without the provision of any additional terminals.
Inventors
- 👤 Jyoji Murakami
- 👤 Tsuyoshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 15:38
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/287; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7842; G06F15/786
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
175 words
A one chip microcomputer comprising: a central processing unit (CPU 1) having arithmetic, logic and control units; a random access memory (RAM 3) for storing intermediate data with instructions processed by the central processing unit (CPU 1); means (4, 23) for carrying first data processed by the central processing unit (CPU 1); a direct memory access controller (DMAC 2) controlled by the central processing unit (CPU 1) for providing'a read out of second data stored in a predetermined area of the random access memory (RAM 3); means (9, 21) for carrying the second data stored in the predetermined area of the random access memory (RAM 3); terminal means (P) coupled to said means for carrying the first and second data to provide an output for the first data during a central processing unit operating mode and for the second data during a direct memory access operating mode; and, a time division means (5) controlled by the direct memory access controller (DMAC 2) for transmitting the first or the second data to the terminal means (P).
Claim 2
Dependent Claim
175 words
A one chip microcomputer comprising: a central processing unit (CPU 1) having arithmetic, logic and control units; a random access memory (RAM 3) for storing intermediate data with instructions processed by the central processing unit (CPU 1); means (4, 23) for carrying first data processed by the central processing unit (CPU 1); a direct memory access controller (DMAC 2) controlled by the central processing unit (CPU 1) for providing'a read out of second data stored in a predetermined area of the random access memory (RAM 3); means (9, 21) for carrying the second data stored in the predetermined area of the random access memory (RAM 3); terminal means (P) coupled to said means for carrying the first and second data to provide an output for the first data during a central processing unit operating mode and for the second data during a direct memory access operating mode; and, a time division means (5) controlled by the direct memory access controller (DMAC 2) for transmitting the first or the second data to the terminal means (P).
Claim 3
Dependent Claim
84 words
A one chip microcomputer according to claim 1, in which the means for carrying first data processed by the central processing unit (CPU 1) comprises an output buffer register (OB4) for storing the first data, and in which the means for carrying the second data is a port means (G 1 , G 2 , G 3 ) for receiving the first data from the output buffer register (OB4) and the second data from a predetermined area of the random access memory (RAM 3).
Claim 4
Dependent Claim
145 words
A one chip microcomputer according to claim 1, in which the means for carrying first data processed by the central processing unit (CPU 1) comprises an output buffer register (OB 4) for storing the first data, and in which the means for parrying the second data is a gate means (G 11, G 19) controlled by the central processing unit (CPU 1) an address port means (13) for transmitting an externally applied address signal to the random access memory (RAM 3) under the control of the gate means (G 11 , G 19 ) so as to read the second data from the random access memory (RAM 3) and port means (G 1 ) for receiving the first data from the output buffer register (OB4) and the second data from the random access memory (RAM 3) when read by the address port means (10, 11).
Claim 5
Dependent Claim
123 words
A one chip microcomputer according to claim 1, in which the means for carrying the first data are formed by a register (21) which is arranged to store the same data as is stored in a predetermined area of the random access memory (RAM 3), the write operation upon the register (21) and upon said predetermined area of the random access memory (RAM 3) being performed simultaneously by the central processing unit (CPU 1), and in which the means for carrying the second data is a parallel-serial converter means (22, 23) controlled by the central processing unit (CPU 1), for converting parallel data into serial data, the parallel data being sent from the register (21) by the direct memory access controller (DMAC 2).
Claim 6
Dependent Claim
74 words
A one chip microcomputer according to claim 1, in which the means for carrying the first and second data is a parallel-serial converter means (22, 23) controlled by the central processing unit (CPU 1), for converting parallel data into serial data,and which also includes an address counter (24) controlled by the direct memory access controller (DMAC 2) for generating an address signal to read the second data from the random access memory (RAM 3).
Claim 7
Dependent Claim
47 words
A one chip microcomputer according to claim 4 or 5, wherein the parallel-serial converter means comprises: a shift register (22) for receiving parallel data; and, a serial input/output circuit(23) controlled by the central processing unit (CPU 1) for performing a shift operation upon the shift register (22).
Claim 8
Dependent Claim
174 words
A one-chip microcomputer comprising: a central processing unit (CPU 1) having arithmetic logic and control units; a random access memory (RAM 2) for storing intermediate data and instructions processed by the central processing unit (CPU 1); an output buffer register (OB4) for storing first data processed by the central processing unit (CPU 1); a direct memory access controller (DMAC 2) controlled by the central processing unit (CPU 1), for reading second data from a predetermined area of the random-access memory (RAM 3); a port means (G) for receiving the first data from the output buffer (OB 4) and the second data from the random access memory (RAM 3) read by the direct memory access controller (DMAC 2); terminals (Pl-7) connected to the port means (G) and used commonly in both the central processing unit operation mode and the direct memory access mode; and, a time division means (5) controlled by the direct memory access controller (DMAC 2) for transmitting the first or the second data through the port means (G) to the terminals (Pl-7).
Claim 9
Dependent Claim
174 words
A one-chip microcomputer comprising: a central processing unit (CPU 1) having arithmetic logic and control units; a random access memory (RAM 2) for storing intermediate data and instructions processed by the central processing unit (CPU 1); an output buffer register (OB4) for storing first data processed by the central processing unit (CPU 1); a direct memory access controller (DMAC 2) controlled by the central processing unit (CPU 1), for reading second data from a predetermined area of the random-access memory (RAM 3); a port means (G) for receiving the first data from the output buffer (OB 4) and the second data from the random access memory (RAM 3) read by the direct memory access controller (DMAC 2); terminals (Pl-7) connected to the port means (G) and used commonly in both the central processing unit operation mode and the direct memory access mode; and, a time division means (5) controlled by the direct memory access controller (DMAC 2) for transmitting the first or the second data through the port means (G) to the terminals (Pl-7).
Claim 10
Dependent Claim
46 words
A one chip microcomputer according to claim 7, further comprising: an address counter (10) controlled by the direct memory access controller (DMAC 2), for generating an address signal so as to read the second data from the predetermined area of the random access memory (RAM 3).
Claim 11
Dependent Claim
67 words
A one chip micorcomputer according to claim 7, further comprising: a gate means (G 11 , G 19 ) controlled by the central processing unit (CPU 1); an address port means (13) for transmitting an externally applied address signal to the random access memory (RAM 3) through the gate means ( G 11 , G 19 ) to read the second data from the random access memory.
Claim 12
Dependent Claim
44 words
A microcomputer according to claim 9, wherein the port means (G l-5 ) comprises bidirectional input/ output ports, through which an externally applied data signal is written into an area of the random access memory (RAM 3) accessed by the address port means (13).
Claim 13
Dependent Claim
141 words
A one chip microcomputer comprising: a central processing unit (CPU) having arithmetic, logic and control units; a random access memory (RAM) for storing intermediate data and instructions processed by said central processing unit; a register for storing the same data as that of a predetermined area of said random access memory, the write operation upon said register and said predetermined area of said random access memory being simultaneously performed by said central processing unit; a direct memory access controller (DMAC) controlled by said central processing unit; a parallel serial converter means, controlled by said central processing unit, for converting parallel data into serial data, said parallel data being sent from said register by said direct memory access controller; and, a terminal connected to said parallel serial converter means and used commonly for the CPU operation mode and the DMA operation mode.
Claim 14
Dependent Claim
141 words
A one chip microcomputer comprising: a central processing unit (CPU) having arithmetic, logic and control units; a random access memory (RAM) for storing intermediate data and instructions processed by said central processing unit; a register for storing the same data as that of a predetermined area of said random access memory, the write operation upon said register and said predetermined area of said random access memory being simultaneously performed by said central processing unit; a direct memory access controller (DMAC) controlled by said central processing unit; a parallel serial converter means, controlled by said central processing unit, for converting parallel data into serial data, said parallel data being sent from said register by said direct memory access controller; and, a terminal connected to said parallel serial converter means and used commonly for the CPU operation mode and the DMA operation mode.
Claim 15
Dependent Claim
131 words
A one chip microcomputer comprising: a central processing unit (CPU) having arithmetic, logic and control units; a random access memory (RAM) for storing intermediate data and instructions processed by said central processing unit; a direct memory access controller (DMAC) controlled by said central processing unit; an address counter, controlled by said direct memory access controller, for generating an address signal so as to read data from said random access memory; a parallel serial converter means, controlled by said central processing unit, for converting parallel data into serial data, the data of said random access memory accessed by said address counter being set in said parallel serial converter means; and, a terminal connected to said parallel serial converter means and used commonly for the CPU operation mode and the DMA operation mode.
Claim 16
Dependent Claim
131 words
A one chip microcomputer comprising: a central processing unit (CPU) having arithmetic, logic and control units; a random access memory (RAM) for storing intermediate data and instructions processed by said central processing unit; a direct memory access controller (DMAC) controlled by said central processing unit; an address counter, controlled by said direct memory access controller, for generating an address signal so as to read data from said random access memory; a parallel serial converter means, controlled by said central processing unit, for converting parallel data into serial data, the data of said random access memory accessed by said address counter being set in said parallel serial converter means; and, a terminal connected to said parallel serial converter means and used commonly for the CPU operation mode and the DMA operation mode.
References Cited (Backward Citations)
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