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EP0037705A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Error correcting memory system

Assignee: Honeywell Inc
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Filing: 1981-04-01
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Granted: —
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Expires: 2001-04-01
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Abstract

Abstract Data from a CPU 2 is fed to a DATA portion of a RAM 22 for storage therein, and to a parity generator PG to generate check bits for storage in a check bit CB portion of RAM 22. To read a word, the data and check bit portions are read into latches 24 and 34. The check bits are compared at 32 with fresh parity bits from 26 generated from the data portion. Decoder 38 detects multiple bit (MB), check bit (CB), and data bit (DB) errors, and the latter two are corrected by Exclusive-OR gate sets 36 and 20 respectively. The corrected data and check bits are written back into the RAM, from gates 20 and via buffer 46 respectively. Thus any errors which occur in the RAM are corrected, instead of being allowed to accumulate. Buffers 28 and 48 allow direct access to the CB part of the RAM and the error correcting circuitry for maintenance.

Inventors

  • 👤 Patrick A. Sedalis

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-27 23:02
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G06F11/1052; G06F11/22; G06F11/2205; G06F11/2215

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 88 words
A memory system comprising a storage unit (22), an ECC (error correcting code) generator (26) which generates an ECC which is stored in the memory unit with a data word, and error detection and correction circuitry (32,38,40, 42,20) which detects and corrects errors in a data word and associated ECC read from the storage unit, characterized in that the corrected data word and associated ECC bits are written back into the storage unit following each read, whereby the accumulation of errors in the data storage unit is inhibited.
Claim 2
Dependent Claim 88 words
A memory system comprising a storage unit (22), an ECC (error correcting code) generator (26) which generates an ECC which is stored in the memory unit with a data word, and error detection and correction circuitry (32,38,40, 42,20) which detects and corrects errors in a data word and associated ECC read from the storage unit, characterized in that the corrected data word and associated ECC bits are written back into the storage unit following each read, whereby the accumulation of errors in the data storage unit is inhibited.
Claim 3
Dependent Claim 60 words
A memory system according to Claim 1, characterized in that the error detection and correction circuitry comprises a comparator (32) fed with the ECC read from the storage unit and a fresh ECC generated from the data word read from the storage unit, and decoder means (38,40,42) which determines the location of any error in the data word and ECC.
Claim 4
Dependent Claim 29 words
A memory system according to Claim 2, characterized in that the decoder means includes a first level decoder (32) which determines whether or not an detected error is correctable.
Claim 5
Dependent Claim 42 words
A memory system according to Claim 3, characterized by second level decoder means (40,42) fed from the first level decoder (38) and comprising first (40) and second (42) decoders which decode the position of errors in the data word and ECC respectively.
Claim 6
Dependent Claim 42 words
A memory system according to any previous claim, characterized by internal timing and control means (12) responsive to instructions from an external source (2) to which the system is connected to control the operation of the system independently of the external source.

References Cited (Backward Citations)

US3735105A Cited
GB1557684A Cited
FR2379880A1 Cited
US4216541A Cited

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