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EP0026083A1
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Multi-processor data processing system
Assignee: Olivetti SpA
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Filing: 1980-09-16
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Granted: —
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Expires: 2000-09-16
Abstract
Abstract A central processor CPU (1) and associated system memory (3) utilise a word length which is a multiple of the word lengths employed by a satellite processor SPU (2) and its memory (4), e.g. 16 bits as against 8 bits. DMA transfers of information are nevertheless possible via a transfer controller (5) including a series of intermediate registers (8,9,10 and 11). To write from memory (4) into system memory (3) for example, two 8-bit words are transferred sequentially from memory (4) to registers (8 and 9). Then the contents of the registers are transferred in parallel as a 16-bit word to the system memory (3). Conversely a 16-bit word can be read from system memory (3) into the registers (10 and 11). Two 8-bit words are then transferred sequentially from these registers to the memory (4).
Inventors
- 👤 Ferdinando Alberto
- 👤 Natale Tos
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 09:00
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
97 words
A multi-processor data processing system comprising at least two memories associated with two different processors, and means for transferring data between said two memories, characterised in that a first memory is capable of memorising words of multiple length with respect to the words of the second memory and said transfer means comprise a plurality of registers corresponding to said multiple and each capable of containing a wore whose length is equal to that of the second memory and control means for controlling the reading or writing of each of said plurality of registers in each transfer operation.
Claim 2
Dependent Claim
97 words
A multi-processor data processing system comprising at least two memories associated with two different processors, and means for transferring data between said two memories, characterised in that a first memory is capable of memorising words of multiple length with respect to the words of the second memory and said transfer means comprise a plurality of registers corresponding to said multiple and each capable of containing a wore whose length is equal to that of the second memory and control means for controlling the reading or writing of each of said plurality of registers in each transfer operation.
Claim 3
Dependent Claim
53 words
A system according to claim 1 characterised in that said transfer means comprise first addressing means which are predisposed at the beginning of an exchange of information comprising at least one transfer in one or other of the two directions, for addressing the regions of said first memory involved in said transfer operations.
Claim 4
Dependent Claim
44 words
A system according to claim 2 characterised in that said first addressing means comprise a counter which is precharged by one of said processors at the beginning of said exchange of information and are counted down by said control means in each completed transfer.
Claim 5
Dependent Claim
41 words
A system according to claim 2 or claim 3 characterised in that said transfer means comprise addressing means which are controlled in each operation of reading or writing performed on the second of said memories for progressively addressing said second memory.
Claim 6
Dependent Claim
29 words
A system according to claim 4 characterised in that said means for addressing said second memory are programmed by said processor at the beginning of said exchange of information.
Claim 7
Independent Claim
119 words
A system according to one of claims 2 to 5 wherein said first memory comprises a series of locations capable of memorising said words, said locations comprising a plurality of sub-regions each capable of containing a part of said words of length equal to that of a word of said second memory, each said location being in correspondence with one of said registers, characterised in that, in each transfer from said first memory to said second memory, said processor programs said control means for controlling the parallel registration of an entire word of said first memory on said registers, the selection of said registers containing said parts and the sequential writing of said words selected on said second memory.
Claim 8
Dependent Claim
40 words
A system according to claim 6 characterised in that said transfer means comprise second addressing means which are programmed by said processor for addressing, within a location of said first memory which is addressed by said addressing means, said sub-region.
Claim 9
Dependent Claim
48 words
A system according to claim 7 characterised in that said sub-regions are two in nymber, two registers of said plurality correspond to said sub-regions, and that said second addressing means selectively activate one of two control signals inputted to said first memory in dependence on the sub-region addressed.
Claim 10
Dependent Claim
63 words
A system according to claim 8 characterised in that in each transfer from said second memory to said first memory, said processor programs and control means for controlling the selection of said registers, the registration of the words read from said second memory on said selected registers and the transfer in parallel of the words from said selected registers to said addressed sub-regions.
Claim 11
Dependent Claim
96 words
A system according to claim 9 characterised in that said control means control a plurality of types of data transfer between said distinct memories according to the direction of the data which are transferred between said memories and according to which of said sub-regions of said location addressed in said first memory are involved in said transfer, and that said control means comprise programmed means containing a plurality of programs, one for each type of transfer, and selection means controlled by said processor for selecting the programs adapted to the type of transfer to be performed.
Claim 12
Independent Claim
75 words
A system according to one of the preceding claims characterised by counting means included in said control means which are predisposed by said processor at the beginning of a plurality of successive information transfer operations and which are counted down in each transfer in reading or writing words of said second memory, said counting means being capable of memorising the number of said transfer operations and signalling completion of said exchange to said control means.
Claim 13
Dependent Claim
63 words
A system according to claim 10 or claim 11 characterised in that, in an exchange of information between said memories comprising at least one of said transfers, said processor controls said selection means for selecting the program relating to the first of said transfers, said control means selecting the programs relating to the successive transfers until said programmed number of transfers is completed.
Claim 14
Dependent Claim
57 words
A system according to claim 12 characterised by a plurality of interrupt signals each of which is adapted to signal the occurrence of an anomalous condition in the transfer operation being performed, and by second selection means responsive to said signals for selecting a series of interrupt programs for generating commands adapted to control said anomalous transfer.
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