US3761697A
Expired / Lapsed
US
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Data processor interface
Assignee: International Standard Electric Corp
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Filing: 1971-11-17
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Granted: 1973-09-25
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Expires: 1991-11-17
Abstract
Abstract An interface is coupled between a 20-bit serial word signalling stem and a 16-bit parallel word data processor. The interface buffers the transmission to an from the line, transfers to and from the processor in pairs of 10-bit half-words, and performs all repetitive functions to limit utilization of the processor.
Inventors
- 👤 K Darton
- 👤 G Hunt
- 👤 D Wright
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:32
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/45; G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
382 words
A data processor interface for connecting a digital data processor utilizing data words of n-bits with a digital data transmission means in which data is transmitted in words of mbits, where m>n but < OR = 2n, the m-bits which make up a transmission word include k check bits, where k < OR = n, the interface comprising in combination: an output section including an m-bit transmitting register from which bits are transmitted to the transmission means in serial form, an m-bit transmitting buffer store and means coupled to enable transferring an m-bit data word in parallel to said transmitting register, a k-bit transmitting check register coupled for receiving the m-bits transmitted from said transmitting register and for forming in response thereto k check bits, means coupling the output of the k-bit check register in the m-bit data word being serially transmitted from the m-bit transmitting register, means including a common set of connecting lines coupled to enable transfer in parallel two n-bit words sequentially to separate portions of the transmitting buffer store from the processor, and means coupled for inserting a test word in the transmitting buffer store in absence of a pair of n-bit data words for transmission from the processor; and an input section including an m-bit receiving register for receiving bits from the transmission means in serial form, an m-bit receiving buffer store coupled for receiving an m-bit data word which is transferred in parallel from said register, a k-bit receiving check register coupled for receiving check bits from the transmission means and for forming check bits, means coupled to the output of the k-bit receiving check register to indicate when the check bits formed are not the same as those received from the transmission means, means coupled to enable transferring in parallel two n-bit data words sequentially from the receiving buffer store to the processor for each m-bit word stored in the buffer store, and each pair of n-bit words having together 2n-m digit positions not occupied by data bitS, gating means for coupling sequentially each of the two n-bit data words from a separate portion of the receiving buffer store to said processor, and means coupled to said register for detecting the presence of a test word entered serially in the register from said transmission means.
Claim 2
Dependent Claim
382 words
A data processor interface for connecting a digital data processor utilizing data words of n-bits with a digital data transmission means in which data is transmitted in words of mbits, where m>n but < OR = 2n, the m-bits which make up a transmission word include k check bits, where k < OR = n, the interface comprising in combination: an output section including an m-bit transmitting register from which bits are transmitted to the transmission means in serial form, an m-bit transmitting buffer store and means coupled to enable transferring an m-bit data word in parallel to said transmitting register, a k-bit transmitting check register coupled for receiving the m-bits transmitted from said transmitting register and for forming in response thereto k check bits, means coupling the output of the k-bit check register in the m-bit data word being serially transmitted from the m-bit transmitting register, means including a common set of connecting lines coupled to enable transfer in parallel two n-bit words sequentially to separate portions of the transmitting buffer store from the processor, and means coupled for inserting a test word in the transmitting buffer store in absence of a pair of n-bit data words for transmission from the processor; and an input section including an m-bit receiving register for receiving bits from the transmission means in serial form, an m-bit receiving buffer store coupled for receiving an m-bit data word which is transferred in parallel from said register, a k-bit receiving check register coupled for receiving check bits from the transmission means and for forming check bits, means coupled to the output of the k-bit receiving check register to indicate when the check bits formed are not the same as those received from the transmission means, means coupled to enable transferring in parallel two n-bit data words sequentially from the receiving buffer store to the processor for each m-bit word stored in the buffer store, and each pair of n-bit words having together 2n-m digit positions not occupied by data bitS, gating means for coupling sequentially each of the two n-bit data words from a separate portion of the receiving buffer store to said processor, and means coupled to said register for detecting the presence of a test word entered serially in the register from said transmission means.
Claim 3
Dependent Claim
30 words
The interface according to claim 1 including means coupled for detecting a received synchronizing word, and means responsive to said synchronizing word for synchronizing the interface with the transmission means.
Claim 4
Dependent Claim
364 words
A data processor interface for connecting a digital data processor utilizing data words of 16 bits with a digital data transmission means in which data is transmitted in words of 20 bits plus k-check bits, the interface comprising in combination: an output section including a 20-bit transmitting register from which bits are transmitted to the transmission means in serial form, a 20-bit transmitting buffer store and means coupled to enable transferring a 20-bit data word in parallel to said transmitting register, a k-bit transmitting check register coupled for forming a k-check bits in response to the data bits, means coupling the output of the k-bit check register in the 20-bit data word being serially transmitted from the 20-bit transmitting register, means including a common set of lines coupled to enable transfer in parallel two 10-bit data words sequentially to separate portions of the transmitting buffer store from the processor, and means coupled for inserting a test word in the transmitting buffer store in absence of a pair of 10-bit data words for transmission from the processor; and an input section including a 20-bit receiving register for receiving bits from the transmission means in serial form, a 20-bit receiving buffer store coupled for receiving a 20-bit data word which is transferred in parallel from said register, a k-bit receiving check register coupled for receiving check bits from the transmission means and for forming check bits, means coupled to the output of the k-bit receiving check register to indicate when the check bits formed are different from those received from the transmission means, means coupled to enable transferring in parallel two 10-bit data words sequentially from the receiving buffer store to the processor for each 20-bit word stored in the buffer store, gating means for coupling sequentially each of the two 10-bit data words from a separate portion of the receiving buffer store to said processor, and means coupled to said register for detecting the presence of a test word entered serially in the register from said transmission means; and said interface including means coupled for detecting a received synchronizing word, and means responsive to said synchronizing word for synchronizing the interface with the transmission means.
Claim 5
Dependent Claim
364 words
A data processor interface for connecting a digital data processor utilizing data words of 16 bits with a digital data transmission means in which data is transmitted in words of 20 bits plus k-check bits, the interface comprising in combination: an output section including a 20-bit transmitting register from which bits are transmitted to the transmission means in serial form, a 20-bit transmitting buffer store and means coupled to enable transferring a 20-bit data word in parallel to said transmitting register, a k-bit transmitting check register coupled for forming a k-check bits in response to the data bits, means coupling the output of the k-bit check register in the 20-bit data word being serially transmitted from the 20-bit transmitting register, means including a common set of lines coupled to enable transfer in parallel two 10-bit data words sequentially to separate portions of the transmitting buffer store from the processor, and means coupled for inserting a test word in the transmitting buffer store in absence of a pair of 10-bit data words for transmission from the processor; and an input section including a 20-bit receiving register for receiving bits from the transmission means in serial form, a 20-bit receiving buffer store coupled for receiving a 20-bit data word which is transferred in parallel from said register, a k-bit receiving check register coupled for receiving check bits from the transmission means and for forming check bits, means coupled to the output of the k-bit receiving check register to indicate when the check bits formed are different from those received from the transmission means, means coupled to enable transferring in parallel two 10-bit data words sequentially from the receiving buffer store to the processor for each 20-bit word stored in the buffer store, gating means for coupling sequentially each of the two 10-bit data words from a separate portion of the receiving buffer store to said processor, and means coupled to said register for detecting the presence of a test word entered serially in the register from said transmission means; and said interface including means coupled for detecting a received synchronizing word, and means responsive to said synchronizing word for synchronizing the interface with the transmission means.
Claim 6
Dependent Claim
15 words
The interface of claim 3, wherein said data word is transmitted with 8 check bits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-24 | 1977-03-26 | 1977-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-24 | 1981-03-26 | 1981-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-24 | 1985-03-26 | 1985-09-25 | $7700.00 | Window Closed / Lapsed |