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DE3918924A1
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DE
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SEMICONDUCTOR MEMORY DEVICE OF THE STACKED CONDENSER TYPE AND MANUFACTURING METHOD THEREFOR
Assignee: Mitsubishi Electric Corp
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Filing: 1989-06-09
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Granted: —
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Expires: 2009-06-09
Abstract
Abstract A storage capacitor in a semiconductor dynamic random access memory (DRAM) comprises a semiconductor substrate (1) having a conductive channel region (24), an insulating oxide layer (25) and an electrode (28a) formed on the substrate, a dielectric layer (29) covering the electrode and a second electrode (30) formed on the dielectric layer. Pref. the capacitor (28a, 29, 30) has raised parallel wall protrusions formed over the channel (24), gate electrode (26) and word line (27) of a transistor. A bit line (42), forming a bridge over the device, is fabricated by a sputter process.
Inventors
- 👤 Wataru Wakamiya
- 👤 Yoshinori Tanaka
- 👤 Takahisa Eimori
- 👤 Hiroji Ozaki
- 👤 Hiroshi Kimura
- 👤 Shinichi Satoh
Bibliographic Details
Application Number
—
Jurisdiction
DE
Data Source
google_patents
Last Synchronized
2026-10-30 10:48
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318
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References Cited (Backward Citations)
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