Patent UST955006I4 successfully refreshed from Google Patents.
UST955006I4
Expired / Lapsed
US
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Delay circuits using negative resistance CMOS circuits
Assignee: International Business Machines Corp
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Filing: 1976-06-14
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Granted: 1977-02-01
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Expires: 1996-06-14
Abstract
Abstract A negative resistance circuit constructed of complementary field effect transistors has several applications. A voltage change at an input to the negative resistance circuit alters the current at the input node in a direction inverse to that normally caused by such a voltage change. The circuit can be used to speed up the charging or the discharging of a circuit node capacitance.
Inventors
- 👤 Joseph Richard Cavaliere
- 👤 David Barry Eardley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:55
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/04; H03K17/041; H03K17/0416; H03K17/04163; H03H; H03H1/00; H03H11/00; H03H11/46; H03H11/52; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565; H03K5/00; H03K5/01; H03K5/02; H03K5/023; H04; H04B; H04B3/00; H04B3/02; H04B3/04; H04B3/16; H04B3/18
Claims Analysis
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References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-02-01 | 1980-08-02 | 1981-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-02-01 | 1984-08-02 | 1985-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-02-01 | 1988-08-02 | 1989-02-01 | $7700.00 | Window Closed / Lapsed |