Process for selecting circuits with optimum
Abstract
Abstract THIS IS AN AUTOMATIC PROCESS FOR SELECTING CIRCUITS TO BE PLACED ON A LARGE SCALE INTEGRATED (LSI) CIRCUIT CLIP. THE PROCESS SELECTS A MINIMUM CIRCUIT SIZE WHICH SATISFIES THE POWER AND TIMING REQUIREMENTS OF THE INDIVIDUAL CIRCUITS ON THE CHIP. MINIMIZATION IS ACHIEVED BY SELECTING FROM USER SPECIFICATION LISTS, THAT CIRCUIT WHICH SATISFIES THE REQUIREMENTS. THE LARGE SCALE INTEGRATED CIRCUIT CHIP RESULTING FROM THE DESIGN PROCESS CONTAINS FIELD EFFECT TRANSISTOR CIRCUITS OF DIFFERENT PHYSICAL SIZE. BY MATCHING THE REQUIRED POWER AND TIMING WITH A STATIONARY CIRCUIT, THE LSI CHIP IS MORE HIGHLY COMPACTED IN THE NUMBER OF CIRCUITS AND PERFORMANCE AVAILABLE WITHIN THE CHIP STRUCTURE.
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