USRE32945E
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronization system for digital data
Assignee: Boeing North American Inc
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Filing: 1987-02-12
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Granted: 1989-06-06
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Expires: 2007-02-12
Abstract
Abstract A digital signal synchronization system including a digital signal source for supplying an input digital signal, and a plurality of substantially identical integrating circuits, each connected to the digital signal source for integrating the signal for a predetermined time. A plurality of clock sources are also provided, each connected to a corresponding one of the integrating circuits, so that each integrating circuit begins integrating the digital signal at a different time. Decision circuits are connected to the output of each of the integrating circuits for electing one of the integrating circuits according to a predetermined criteria.
Inventors
- 👤 Richard A. Smithson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 03:58
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
199 words
A digital signal synchronization system comprising: a signal source for supplying an input signal; an analog to digital converter having an input connected to said signal source; and an output; a plurality of substantially identical .[.summing circuits.]. .Iadd.integrators, .Iaddend.each connected to said output of said analog to digital converter for summing a plurality of successive signals for a predetermined time; a plurality of clock sources.Iadd., .Iaddend.each connected to a corresponding one of said 171 summing circuits.]. .Iadd.integrators .Iaddend.so that each .[.summing circuit.]. .Iadd.integrator .Iaddend.begins summing said digital signal beginning at a different time; .[.and.]. .Iadd.a plurality of memories, each of which is coupled to one of said integrators for storing a plurality of words, each of said words being representative of an output of the associated integrator; a plurality of summing circuits, each of which is coupled to one of said memories for combining words from said memory; and .Iaddend. decision means connected to the output of each of said summing circuits for selecting one of said summing circuits according to a predetermined criteria, so that said clock signal associated with said one of said summing circuits is selected as the synchronized clock signal associated with said input signal.
Claim 2
Dependent Claim
199 words
A digital signal synchronization system comprising: a signal source for supplying an input signal; an analog to digital converter having an input connected to said signal source; and an output; a plurality of substantially identical .[.summing circuits.]. .Iadd.integrators, .Iaddend.each connected to said output of said analog to digital converter for summing a plurality of successive signals for a predetermined time; a plurality of clock sources.Iadd., .Iaddend.each connected to a corresponding one of said 171 summing circuits.]. .Iadd.integrators .Iaddend.so that each .[.summing circuit.]. .Iadd.integrator .Iaddend.begins summing said digital signal beginning at a different time; .[.and.]. .Iadd.a plurality of memories, each of which is coupled to one of said integrators for storing a plurality of words, each of said words being representative of an output of the associated integrator; a plurality of summing circuits, each of which is coupled to one of said memories for combining words from said memory; and .Iaddend. decision means connected to the output of each of said summing circuits for selecting one of said summing circuits according to a predetermined criteria, so that said clock signal associated with said one of said summing circuits is selected as the synchronized clock signal associated with said input signal.
Claim 3
Dependent Claim
28 words
A system as defined in claim 1, wherein said decision means functions to select said one of said summing circuits having the output with the greatest absolute value.
Claim 4
Dependent Claim
19 words
A system as defined in claim 1, wherein said summing circuits comprises an adder and a shifter register memory.
Claim 5
Dependent Claim
26 words
A system as defined in claim 1, wherein each of said clock sources has a frequency identical with the digital data rate of the input signal.
Claim 6
Dependent Claim
17 words
A system as defined in claim 1, wherein each of said clock sources has a different phase.
Claim 7
Dependent Claim
176 words
A digital signal synchronization system comprising: a signal source for supplying an input signal; an analog to digital converter having an input connected to said signal source; and an output; a plurality of substantially identical summing circuits.Iadd., .Iaddend.each connected to said output of said analog to digital convertor for summing a plurality of successive signals for a predetermined time; a plurality of clock sources.Iadd., .Iaddend.each connected to a corresponding one of said summing circuits so that each summing circuit begins summing said digital signal beginning at a different time; decision means connected to the output of each of said summing circuits for selecting one of said summing circuits according to a predetermined criteria so that said clock signal associated with said one of said summing circuits is selected as the synchronized clock signal associated with said input signal; and .Iadd.each of .Iaddend.said summing circuits .[.comprise.]. .Iadd.comprises .Iaddend.an adder and a shift register memory, .Iadd.and said shift register memory stores a plurality of words, each of said words being representative of the output of the associated adder.Iaddend..
Claim 8
Dependent Claim
176 words
A digital signal synchronization system comprising: a signal source for supplying an input signal; an analog to digital converter having an input connected to said signal source; and an output; a plurality of substantially identical summing circuits.Iadd., .Iaddend.each connected to said output of said analog to digital convertor for summing a plurality of successive signals for a predetermined time; a plurality of clock sources.Iadd., .Iaddend.each connected to a corresponding one of said summing circuits so that each summing circuit begins summing said digital signal beginning at a different time; decision means connected to the output of each of said summing circuits for selecting one of said summing circuits according to a predetermined criteria so that said clock signal associated with said one of said summing circuits is selected as the synchronized clock signal associated with said input signal; and .Iadd.each of .Iaddend.said summing circuits .[.comprise.]. .Iadd.comprises .Iaddend.an adder and a shift register memory, .Iadd.and said shift register memory stores a plurality of words, each of said words being representative of the output of the associated adder.Iaddend..
Claim 9
Dependent Claim
31 words
A system as defined in claim 6, wherein said clock signal associated with said one of said summing circuits is selected as the synchronized clock signal associated with said input signal.
Claim 10
Dependent Claim
26 words
A system as defined in claim 6, wherein each of said clock sources has a frequency identical with the digital data rate of the input signal.
Claim 11
Dependent Claim
17 words
A system as defined in claim 6, wherein each of said clock sources has a different phase.
Claim 12
Dependent Claim
174 words
A digital signal synchronization system comprising: a digital signal source for supplying an input digital signal; a plurality of substantially identical integrating circuits.Iadd., .Iaddend.each connected to said digital signal source for integrating the signal for a predetermined time; a plurality of clock sources.Iadd., .Iaddend.each connected to a corresponding one of said integrating circuits so that each integrating circuit begins integrating said digital signal at a different time; and .Iadd.a plurality of memories, each of which is coupled to one of said integrators for storing a plurality of words, each of said words being representative of the output of the integrator; a plurality of summing circuits, each of which is coupled to one of said memories for combining words from said memory; and .Iaddend. decision means connected to the output of each of said 171 integrating.]. .Iadd.summing .Iaddend.circuits for selecting one of said .[.integrating.]. .Iadd.summing .Iaddend.circuits .Iadd.and its associated integrating circuit .Iaddend.such that said clock signal associated with said one of said integrating circuits is the synchronized clock signal associated with said input digital signal.
Claim 13
Dependent Claim
174 words
A digital signal synchronization system comprising: a digital signal source for supplying an input digital signal; a plurality of substantially identical integrating circuits.Iadd., .Iaddend.each connected to said digital signal source for integrating the signal for a predetermined time; a plurality of clock sources.Iadd., .Iaddend.each connected to a corresponding one of said integrating circuits so that each integrating circuit begins integrating said digital signal at a different time; and .Iadd.a plurality of memories, each of which is coupled to one of said integrators for storing a plurality of words, each of said words being representative of the output of the integrator; a plurality of summing circuits, each of which is coupled to one of said memories for combining words from said memory; and .Iaddend. decision means connected to the output of each of said 171 integrating.]. .Iadd.summing .Iaddend.circuits for selecting one of said .[.integrating.]. .Iadd.summing .Iaddend.circuits .Iadd.and its associated integrating circuit .Iaddend.such that said clock signal associated with said one of said integrating circuits is the synchronized clock signal associated with said input digital signal.
Claim 14
Dependent Claim
29 words
A system as defined in claim 10, wherein said decision means functions to select said one of said .[.integrating.]. .Iadd.summing .Iaddend.circuits having the output with the greatest absolute value.
Claim 15
Dependent Claim
17 words
A system as defined in claim 10, when said integrating circuits comprises integrate and dump matched filters.
Claim 16
Dependent Claim
26 words
A system as defined in claim 10, wherein each of said clock sources has a frequency identical with the data rate of the input digital signal.
Claim 17
Dependent Claim
17 words
A system as defined in claim 10, wherein each of said clock sources has a different phase.
Claim 18
Dependent Claim
37 words
A system as defined in claim 10, further comprising convolving means connected to the output of said selected one of said .[.integrating.]. .Iadd.summing .Iaddend.circuits for computing a convolution function signal using the output signal on said output.
Claim 19
Dependent Claim
51 words
A system as defined in claim 10, further comprising threshold detection means connected to the output of said selected one of said .[.integrating.]. .Iadd.summing .Iaddend.circuits for sensing the output signal on said output and producing an activating signal if the magnitude of said output signal exceeds a predetermined threshold signal magnitude.
Claim 20
Dependent Claim
32 words
A system as defined in claim 10, wherein said .[.integrating circuit comprises a serial.]. memory .Iadd.is .Iaddend.for storing a plurality of words in information representing the successive integrations of said input signal.
References Cited (Backward Citations)
US3474342A
Cited
US3502905A
Cited
US3602826A
Cited
US3716780A
Cited
US3786491A
Cited
US3851101A
Cited
US4074073A
Cited
US4007330A
Cited
US4088833A
Cited
US4012598A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-05 | 1992-12-05 | 1993-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-05 | 1996-12-05 | 1997-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-05 | 2000-12-05 | 2001-06-06 | $7700.00 | Window Closed / Lapsed |