Data processing unit with pipelined operands

Claim 2

A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations, comprising: (A) instruction fetch means connected to memory means for storing instructions and operands, said instruction fetch means including, (1) instruction prefetch means for prefetching and retaining instructions from said memory means, and (2) instruction alignment means for aligning bit sequences of instructions including at least one operand specifier prefetched from said memory means; (B) instruction decoding means connected to said instruction fetch means, said instruction decoding means including, (1) a first operand specifier decoding means and a second operand specifier decoding means both connected to said instruction alignment means, said second operand specifier decoding means being capable of decoding a next sequential operand specifier received from said instruction alignment means in the same machine cycle as a first operand specifier; and (2) operation code decoding means connected to said instruction alignment means for ascertaining the operand specifiers included in the instruction from said instruction alignment means and ascertaining the function of said instruction, said .[.operand.]. .Iadd.operation code .Iaddend.decoding means including a simultaneous decode permission means for issuing a signal to permit simultaneous decoding of two operand specifiers within the same machine cycle, said permission signal being provided to said second operand specifier decoding means, said second operand specifier decoding means decoding the next sequential operand specifier to the operand specifier decoded by said first operand specifier decoding means only when said permission signal is provided thereto; and (C) address calculation means connected to said instruction decoding means for calculating an effective address of the operand in accordance with information of an operation code and operand specifiers decoded by said instruction decoding means in the previous machine cycle, whereby said instruction fetch means, said instruction decoding means and said address calculation means carry out their processes in parallel, and said instruction decoding means and said address calculation means carry out their process for each operand specifier.

Claim 3

A data processing unit according to claim 1 wherein said simultaneous decode permission means provides said permission signal only when said second operand specifier decoding means is in a register designation mode.

Claim 4

A data processing unit according to claim 1, wherein said instruction prefetch means includes: (1) instruction buffer means connected to said memory means, said instruction buffer means retaining instructions prefetched from said memory means, and (2) a fetch pointer connected to said memory means for applying to said memory means an address of an instruction to be prefetched to said instruction buffer means.

Claim 5

A data processing unit according to claim 3, wherein said instruction decoding means further includes a decode pointer means for pointing to a leading address to be decoded, and wherein said instruction fetch means includes alignment means connected to an instruction buffer means and said decode pointer for aligning sequential data from the address of said instruction buffer means pointed to by said decode pointer such that said data includes at least one operand specifier.

Claim 6

A data processing unit according to claim 3, wherein said instruction prefetch means further includes: instruction fetch control means connected to said memory means, said instruction fetch control means prefetching an instruction from said memory when said instruction buffer means has a vacant area.

Claim 7

A data processing unit according to claim 2, wherein said instruction decoding means further includes: a decode pointer means for pointing to a leading address to be decoded, and wherein said instruction fetch means includes alignment means connected to an instruction buffer means and said decode pointer, said alignment means aligning sequential data from the address of said instruction buffer means pointed to by said decode pointer such that said data includes operation codes and at least one operand specifier in a first decode cycle of an instruction, and at least one operand specifier in a subsequent decode cycle of the instruction.

Claim 8

A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations, comprising: (A) instruction fetch means connected to memory means for storing instructions and operands, said instruction fetch means including: (1) instruction buffer means connected to said memory means, for retaining instructions prefetched from said memory means, (3) a fetch pointer connected to said memory means for applying to said memory means an address of an instruction to be prefetched into said instruction buffer means, and (3) instruction alignment means connected to said instruction buffer means, for aligning bit sequences of instructions prefetched from said memory means in the order of their address, for outputting a bit sequence including an operation code and at least one operand specifier in a first decode cycle, and for outputting a bit sequence including at least one operand specifier in a succeeding decode cycle; (B) instruction decoding means connected to said instruction fetch means, said instruction decoding means including: (1) operation code decoding means connected to said instruction alignment means for ascertaining the operand specifiers included in instruction aligned by said instruction alignment means and ascertaining the function of said instruction, and (2) operand specifier decoding means connected to said instruction alignment means for decoding one or more operand specifiers aligned by said instruction alignment means in the same machine cycle, and (C) address calculation means connected to said decoding means for calculating an effective address of the operand in accordance with an operation code and operand specifiers decoded by said decoding means in the previous machine cycle, whereby said instruction fetch means carries out instruction fetching independently of the instruction decoding means and of the address calculation means, said instruction decoding means operates, utilizing an operand specifier as a basic processing unit of, independently of the instruction fetch means and of the address calculation means, and said address calculation means operates, utilizing an operand specifier as a basic unit of processing, independently of the instruction fetch means and of the instruction decoding means, thereby carrying out pipelined processing based on a unit of one or more than one simultaneously processed operand specifiers.

Claim 9

A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations, comprising: (A) instruction fetch means connected to memory means for storing instructions and operands, said instruction fetch means including: (1) instruction buffer means connected to said memory means, for retaining instructions prefetched from said memory means, (3) a fetch pointer connected to said memory means for applying to said memory means an address of an instruction to be prefetched into said instruction buffer means, and (3) instruction alignment means connected to said instruction buffer means, for aligning bit sequences of instructions prefetched from said memory means in the order of their address, for outputting a bit sequence including an operation code and at least one operand specifier in a first decode cycle, and for outputting a bit sequence including at least one operand specifier in a succeeding decode cycle; (B) instruction decoding means connected to said instruction fetch means, said instruction decoding means including: (1) operation code decoding means connected to said instruction alignment means for ascertaining the operand specifiers included in instruction aligned by said instruction alignment means and ascertaining the function of said instruction, and (2) operand specifier decoding means connected to said instruction alignment means for decoding one or more operand specifiers aligned by said instruction alignment means in the same machine cycle, and (C) address calculation means connected to said decoding means for calculating an effective address of the operand in accordance with an operation code and operand specifiers decoded by said decoding means in the previous machine cycle, whereby said instruction fetch means carries out instruction fetching independently of the instruction decoding means and of the address calculation means, said instruction decoding means operates, utilizing an operand specifier as a basic processing unit of, independently of the instruction fetch means and of the address calculation means, and said address calculation means operates, utilizing an operand specifier as a basic unit of processing, independently of the instruction fetch means and of the instruction decoding means, thereby carrying out pipelined processing based on a unit of one or more than one simultaneously processed operand specifiers.

Claim 10

A data processing unit according to claim 7, wherein said instruction fetch means includes instruction fetch control means connected to said memory means and said instruction decoding means for fetching an instruction from said memory means when there occurs a vacant area in said instruction buffer means, comparing the effective data length of the vacant area in said instruction buffer means with the data length necessary to a decoding operation, and giving permission for decoding to said decoding means.

Claim 11

A data processing unit according to claim 8, wherein said instruction decoding means further includes: (1) a decode pointer connected to said instruction fetch control means for applying a leading address to be decoded to said instruction fetch control means and to said instruction alignment means, (2) instruction decode length calculation means connected to said instruction fetch control means for calculating the length of instruction to be decoded and providing the calculated length to said instruction fetch control means, and (3) decoding control means connected to said instruction fetch control means and said address calculation means for receiving signals from said instruction fetch control means and said address calculation means to control the overall operation of said decoding means.

Claim 12

A data processing unit according to claim 8, wherein said decode length calculating means calculates the sum of the length of the operation code and the length of the operand specifier of the first operand following the operation code when the operation code is included in the decoding process, and calculates the length of an operand specifier when the operation code is not included in the decoding process, and provides the calculated length to said instruction fetch control means.

Claim 13

A data processing unit according to claim 9 wherein said instruction diode length calculation means includes means operative, when the simultaneous decode of two operand specifiers is permitted, to further add the length of an operand specifier of a register designation mode and provide the resulting sum to said instruction control means.

Claim 14

A data processing unit according to claim 9, wherein said instruction decoding means further includes: address calculation program counter value calculation means connected to said instruction fetch means and said address calculation means, said address calculation program counter value calculation means calculating a program counter value used in the address calculation in a program relative mode of an operand specifier to be decoded, based on the decode results from said operation code decoding means and said operand specifier decoding means and the information of the leading address to be decoded from said decode pointer, and providing the calculated count to said address calculation means.

Claim 15

A data processing unit according to claim 9, wherein said alignment means includes a multi-bit shifter capable of shifting a plurality of bits simultaneously, the number of times of shift being indicated by said decode pointer.

Claim 16

A data processing unit according to claim 9, wherein said address calculation means includes: (1) decode result retaining means connected to said instruction decoding means, said decode result retaining means retaining information decoded by said instruction decoding means, (2) calculation means connected to said decode result retaining means, said calculation means calculating an execution address of an operand, based on the information from said decode result retaining means, and (3) address calculation control means connected to said decoding control means, said address calculation control means being operative when a decode result for at least one operand specifier is loaded to said decode result retaining means for causing said calculation means to calculate the effective address of the operand based on the decode result and providing to said decoding control means information indicating whether the decode result can be loaded to said decode result retaining means.

Claim 17

A data processing unit according to claim 14, wherein said decode result retaining means includes: (1) control data latch means for latching control data necessary to calculate the address, (2) register address latch means for latching register addresses included in an operand specifier, (3) displacement latch means for latching displacement, literal data and absolute address information included in an operand specifier and (4) address calculation start signal latch means for latching a signal indicating the start of the address calculation of an operand based on the decode result.

Claim 18

A data processing unit according to claim 9 wherein said instruction decoding means further includes: (1) decode pointer updating means connected to said decode pointer, said decode pointer updating means adding to the content of said decode pointer the length of an instruction decoded in the decode cycle and sending the resulting sum to said decode pointer as a leading address to be decoded next, and (2) instruction decode length calculation means connected to said operation code decoding means and said first operand specifier decoding means, said instruction length calculation means calculating a sum of the length of the operation code and the length of an operand specifier of a first operand following to the operation code in a decode cycle including the operation code and calculating the length of the operand specifier in a decoding cycle including no operation code and presenting the calculated length to said decode pointer updating means as a decoded instruction length.

Claim 19

A data processing unit according to claim 16 wherein said instruction decode length calculation means includes means operative, when the simultaneous decode of the two operands is permitted, to further add the length of the operand specifier of the register designation mode and provide the resulting sum to said decode pointer updating means. .Iadd.

Claim 20

A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations, comprising: first means for storing data including variable length instructions and certain of the operands to be executed by certain of the instructions; second means for prefetching an instruction from said first means, for retaining the prefetched instruction, and for aligning a predetermined sequence of elements of the instruction including at least one operand specifier; third means for decoding an operation code and each operand specifier of an aligned instruction received from said second means, for calculating the effective address for the operand specified by each operand specifier in accordance with the decoded operation code, for fetching the operand from said first means in accordance with the calculated effective address for each operand specifier, and for retaining the fetched operands; fourth means for controlling said third means so that said decoding and said address calculating are executed independently and at different times for each operand specifier, with one operand specifier being decoded while an effective address for an operand corresponding to another preceding operand specifier is being calculated; and fifth means for executing the instruction in accordance with the decoded operation code and the retained operand. .Iaddend. .Iadd.

Claim 21

A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations, comprising: first means for storing data including variable length instructions and certain of the operands to be executed by certain of the instructions; second means for prefetching an instruction from said first means, for retaining the prefetched instruction, and for aligning a predetermined sequence of elements of the instruction including at least one operand specifier; third means for decoding an operation code and each operand specifier of an aligned instruction received from said second means, for calculating the effective address for the operand specified by each operand specifier in accordance with the decoded operation code, for fetching the operand from said first means in accordance with the calculated effective address for each operand specifier, and for retaining the fetched operands; fourth means for controlling said third means so that said decoding and said address calculating are executed independently and at different times for each operand specifier, with one operand specifier being decoded while an effective address for an operand corresponding to another preceding operand specifier is being calculated; and fifth means for executing the instruction in accordance with the decoded operation code and the retained operand. .Iaddend. .Iadd.

Claim 22

A data processing unit according to claim 18, wherein said fourth means includes means for controlling the decoding by said third means so as to decode two operand specifiers simultaneously in case of a last operand specifier of the instruction having a register mode and for controlling said address calculation by said third means so as to not calculate the effective address for the operand corresponding to the register mode operand specifier, the decoded data of the register mode operand specifier being treated as the effective address for the register directly. .Iaddend. .Iadd.20. A data processing unit according to claim 18, wherein said third means includes means for providing a two operand specifier decoding permission signal in response to certain operation codes, and said fourth means includes means for controlling the decoding by said third means so as to decode two operand specifiers simultaneously when said two operand specifier decoding permission signal is provided and the last operand specifier of the instruction is in a register mode, and for controlling said address calculation by said third means so as to not calculate the effective address for the operand corresponding to the register mode operand specifier, the decoded data of the register mode operand specifier being treated as the effective address for the register

Claim 23

directly. .Iaddend. .Iadd.21. A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations, comprising: first means for storing data including variable length instructions and certain of the operands to be executed by certain of the instructions; second means for accessing said first means to exchange data with said first means; third means for prefetching an instruction from said second means, for retaining the prefetched instruction, and for aligning a predetermined sequence of elements of the instruction including at least one operand specifier; fourth means for decoding an operation code and each operand specifier of an aligned instruction received from said third means, for calculating the effective address for the operand specified by each operand specifier in accordance with the decoded operation code, for fetching the operand from said second means in accordance with the calculated effective address for each operand specifier, and for retaining the fetched operands; fifth means for controlling said fourth means so that said decoding and said address calculating are executed independently and at different times for each operand specifier, with one operand specifier being decoded while an effective address for an operand corresponding to another preceding operand specifier is being calculated; and sixth means for executing the instruction in accordance with the decoded operation code and the retained operand. .Iaddend. .Iadd.22. A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operand codes for ascertaining operations, comprising: (A) instruction fetch means connected to memory means for storing instructions and operands, said instruction fetch means including, (1) instruction prefetch means for prefetching and retaining instructions from said memory means, and (2) instruction alignment means for aligning bit sequences of instructions including at least one operand specifier prefetched from said memory means; (B) instruction decoding means connected to said instruction fetch means, said instruction decoding means including, (1) operand specifier decoding means connected to said instruction alignment means for decoding a next sequential operand specifier received from said instruction alignment means simultaneously with a preceding operand specifier and (2) operation code decoding means connected to said instruction alignment means for decoding the operation code included in the instruction from said instruction alignment means and ascertaining the function of said instruction, said operation code decoding means including a simultaneous decode permission means for issuing a signal to permit simultaneous decoding of two operand specifiers within the same machine cycle, said permission signal being provided to said operand specifier decoding means to permit the decoding of the next sequential operand specifier simultaneously with decoding of the preceding operand specifier, and (C) address calculation means connected to said instruction decoding means for calculating an effective address of the operand in accordance with information of an operation code and operand specifiers decoded by said instruction decoding means in the previous machine cycle, whereby said instruction fetch means, said instruction decoding means and said address calculation means carry out their processes in parallel, and said instruction decoding means and said address calculation means carry out their process for each operand specifier. .Iaddend. .Iadd.23. A data processing unit according to claim 22 wherein said operand specifier decoding means operates to decode the next sequential operand specifier simultaneously with the decoding of the preceding operand specifier only when said permission signal is provided thereto and the addressing mode of said next sequential operand specifier is a register mode. .Iaddend.