Digital-to-analog converter and PCM encoder using the converter

Claim 2

A digital-to-analog converter comprising: a capacitor array circuit including first to eighth capacitors having binary-weighted capacities in ratio, each capacitor having one end thereof connected to an output line, a first common line of a first potential connected to the other ends of said first to eighth capacitors through respective switch contacts of a first switch group, a second common line of a second potential connected to the other ends of said first to seventh capacitors through respective switch contacts of a second switch group, and a third common line connected to the other ends of said first to eighth capacitors through respective switch contacts of a third switch group; a resistor string circuit including a resistance element connected between said second common line and a source of said first potential, sixteen taps connected to said resistance element at respective points for deriving voltages which correspond to (2n-1)/33 (where n represents a given number of 1 to 16) of a voltage applied across said resistance element, and a fourth switch group including a plurality of switches inserted between said third common line and said taps, respectively; and logic circuit means for controlling selectively the switching operation of said first to fourth switch groups in dependence on a digital signal to be converted, thereby to produce an analog voltage corresponding to the digital signal from said output line.

Claim 3

A digital-to-analog converter according to claim 1, wherein said logic circuit means includes a first logic circuit for controlling the switching operation of the switches of said first, second and third switch groups and a second logic circuit for controlling the switching operation of the switches of said fourth switch group, said first logic circuit including means for producing signals for controlling the switches of said first, second and third switch groups in dependence on values of the second to eighth bits of an eight-bit digital signal in which a first bit is a polarity bit, while said second logic circuit includes means for producing signals for controlling the switches of said fourth switch group in dependence on values of the fifth to eighth bits of said digital signal.

Claim 4

A digital-to-analog converter according to claim 2, wherein said second logic circuit is adapted to produce the switch control signal in such a manner that, when the decimal digit value n represented by said fifth to eighth bits of said digital signal corresponds to a given one of the values 1 to 15, one of the switches of said fourth switch group at the n-th positions is turned on, while the switch of said fourth switch group at the n-th position where n=16 is turned on when all of said fifth to eighth bits are zero.

Claim 5

A digital-to-analog converter according to claim 3, wherein said first logic circuit is adapted to produce said switch control signals in such a manner that, when at least one bit of said fifth to eighth bits is logic "1", the capacitors inclusive of said first capacitor to the capacitor located at a position which corresponds to a decimal digit value m represented by said second to fourth bits are connected to said second common line, while the (m+1)-th capacitor is connected to said third common line with the remaining capacitor(s) being connected to said first common line, and when said fifth to eighth bits are all logic "0's", the capacitor at the position corresponding to the decimal digit value m represented by said second to fourth bits is connected to said third common line, while said first to the (m-1)-th capacitors are connected to said second common line with the remaining capacitor(s) being connected to said first common line.

Claim 6

A PCM encoder comprising: a voltage comparator for comparing a voltage at an input terminal with a first potential; a capacitor array circuit including first to eighth capacitors having binary-weighted capacitances in ratio and each having one end thereof connected in common to said input terminal of said voltage comparator, a first common line connected to the other ends of said first to eighth capacitors through respective switches of a first switch group, a second common line connected to the other ends of said first to seventh capacitors through switches of a second switch group, a third common line connected to the other ends of said first to eighth capacitors through switches of a third switch group, and means for changing over said input terminal of said voltage comparator to said first potential and said first common line to a sample signal input terminal in response to the input of a sample signal and for changing over said input terminal of said voltage comparator to a free potential and said first common line to said first potential for an encoding operation; a resistor string circuit including a resistance element connected between said second common line and a source of said first potential, sixteen taps connected to said resistance element at respective points for deriving voltages which correspond to (2n-1)/33 (where n is a given one of the values 1 to 16) of a voltage applied across said resistance element, and switches of a fourth switch group inserted between said third common line and said taps, respectively; a fifth switch for supplying selectively a reference voltage of positive or negative polarity to said second common line; a successive approximation register circuit for successively and selectively controlling the switches of said first to fourth switch groups and said fifth switch in dependence on the output from said voltage comparator, thereby to convert said sample signal into a corresponding digital signal to be output; and a pulse generator circuit for producing pulses for controlling the operation of said successive approximation register circuit.

Claim 7

A PCM encoder comprising: a voltage comparator for comparing a voltage at an input terminal with a first potential; a capacitor array circuit including first to eighth capacitors having binary-weighted capacitances in ratio and each having one end thereof connected in common to said input terminal of said voltage comparator, a first common line connected to the other ends of said first to eighth capacitors through respective switches of a first switch group, a second common line connected to the other ends of said first to seventh capacitors through switches of a second switch group, a third common line connected to the other ends of said first to eighth capacitors through switches of a third switch group, and means for changing over said input terminal of said voltage comparator to said first potential and said first common line to a sample signal input terminal in response to the input of a sample signal and for changing over said input terminal of said voltage comparator to a free potential and said first common line to said first potential for an encoding operation; a resistor string circuit including a resistance element connected between said second common line and a source of said first potential, sixteen taps connected to said resistance element at respective points for deriving voltages which correspond to (2n-1)/33 (where n is a given one of the values 1 to 16) of a voltage applied across said resistance element, and switches of a fourth switch group inserted between said third common line and said taps, respectively; a fifth switch for supplying selectively a reference voltage of positive or negative polarity to said second common line; a successive approximation register circuit for successively and selectively controlling the switches of said first to fourth switch groups and said fifth switch in dependence on the output from said voltage comparator, thereby to convert said sample signal into a corresponding digital signal to be output; and a pulse generator circuit for producing pulses for controlling the operation of said successive approximation register circuit.

Claim 8

A PCM encoder according to claim 5, wherein said successive approximation register circuit includes means for storing a digital code the contents of which are successively altered by the output signal from said voltage comparator, a first logic circuit for controlling switching operations of the switches of said first to third switch groups, and a second logic circuit for controlling the switching operation of the switches of said fourth switch group.

Claim 9

A PCM encoder according to claim 6, wherein said digital code storing means includes first means for controlling said fifth switch in dependence on the first bit signal output from said voltage comparator and second means adapted to be initialized by a pulse signal supplied from said pulse generator and to store digital values of said second to eighth bits which are successively determined in dependence on the output signal from said voltage comparator, said first logic circuit including means for producing the switch control signal in dependence on values of said second to eighth bits produced from said second means, while said second logic circuit includes means for producing the switch control signal in dependence on the values of said fifth to eighth bits.

Claim 10

A PCM encoder according to claim 7, wherein said second logic circuit is adapted to produce the switch signal in such a manner that, when the decimal digit value n represented by said fifth to eighth bits of said digital signal corresponds to a given one of the values 1 to 15, one of the switches of said fourth switch group at the n-th position is turned on, while the switch of said fourth switch group at the n-th position where n=16 is turned on when all of said fifth to eighth bits are zero.

Claim 11

A PCM encoder according to claim 8, wherein said first logic circuit is adapted to produce said switch control signal in such a manner that, when one of said fifth to eighth bits is logic "1", the capacitors inclusive of said first capacitor to the capacitor located at a position which corresponds to a decimal digit value m represented by said second to fourth bits are connected to said second common line, while the (m+1)-th capacitor is connected to said third common line with the remaining capacitor(s) are connected to said first common line, and when said fifth to eighth bits are all logic "0's", the capacitor at the position corresponding to the decimal digit value m represented by said second to fourth bits is connected to said third common line, while said first to the (m-1)-th capacitors are connected to said second common line with the remaining capacitor(s) being connected to said first common line. .Iadd.

Claim 12

A PCM encoder comprising a voltage comparator for comparing a voltage at an input terminal with a first potential; a capacitor array circuit including first to eighth capacitors having binary-weighted capacitances in ratio and each having one end thereof connected to said input terminal of said comparator, a first common line connected to the other ends of said first to eighth capacitors through respective switches of a first switch group, a second common line connected to the other ends of said first to seventh capacitors through switches of a second switch group, and a third common line connected to the other ends of said first to eighth capacitors through switches of a third switch group; a resistor string circuit including a resistance element connected between a reference voltage source and a source of said first potential, sixteen taps connected to said resistance element at respective points for deriving voltages which correspond to (2n-1)/33 (where n is a given one of the values 1 to 16) of a voltage applied across said resistance element, and switches of a fourth switch group inserted between said third common line and said taps, respectively; means including a fifth switch group for applying a voltage, which corresponds to an input signal to be coded, to each of said first to eighth capacitors during a sampling operation and for applying the voltage of said reference voltage source; between said first and second common lines during an encoding operation; a successive approximation logic circuit means for successively and selectively controlling the switches of said first to fourth switch groups and said fifth switch group, the output of said logic circuit means being dependent on the output from said voltage comparator, thereby to convert said voltage across each of said first to eighth capacitors into a corresponding digital signal to be output; and a pulse generator circuit for producing pulses for controlling the operation of said successive approximation logic circuit means. .Iaddend. .Iadd.11. A PCM encoder according to claim 10, wherein said successive approximation logic circuit means includes a register for storing a digital code the contents of which are successively altered by the output signal from said voltage comparator, a first logic circuit for controlling switching operations of the switches of said first to third switch groups, and a second logic circuit for controlling the switching operation of the switches of said fourth switch group. .Iaddend. .Iadd.12. A PCM encoder according to claim 11, wherein said second logic circuit is adapted to produce the switch signal in such a manner that, when the decimal digit value n represented by said fifth to eighth bits of said digital signal corresponds to a given one of the values 1 to 15, one of the switches of said fourth switch group at the n-th position and when all of said fifth to eighth bits are zero, the switch of said fourth switch group at the 16-th position is turned on. .Iaddend. .Iadd.13. A PCM encoder according to claim 12, wherein said first logic circuit is adapted to produce said switch control signal in such a manner that, when one of said fifth to eighth bits is logic "1", the capacitors inclusive of said first capacitor to the capacitor located at a position which corresponds to a decimal digit value m represented by said second to fourth bits are connected to said second common line while the (m+1)-th capacitor is connected to said third common line with the remaining capacitor(s) are connected to said first common line, and when said fifth to eighth bits are all logic "0's", the capacitor at the position corresponding to the decimal digital value m represented by said second to fourth bits is connected to said third common line, while said first to the (m-1)-th capacitors are connected to said second common line with the remaining capacitor(s) being connected to said first common line. .Iaddend.