Configuration control in multiprocessors

Abstract

Abstract THE PRESENT MULTIPROCESSOR APPARATUS INCLUDES, IN EFFECT, A DISTRIBUTED INTERCONNECTION SYSTEM SUCH THAT FAILURE OF A PORTION PF THE INTERCONNECTION SYSTEM DOES NOT COMPLETELY DISABLE THE APPARATUS. EACH ELEMENT-OF A PLURALITY OF COMPUTING ELEMENTS, A PLURALITY OF STORAGE ELEMENTS, AND A PLURALITY OF OTHER INFORMATION PROCESSING ELEMENTS OF THE TOTAL MULTIPROCESSOR APPARARUS-IS EQUIPPED WITH AN INDIVIDUAL CONFIGURATION CONTROL REGGISTER FOR SELECTIVELY CONTROLLING THE FLOW OF INFORMATION BETWEEN THE RESPECTIVE ELEMENTS AND OTHER ELEMENTS OF THE APPARATUS. FOR CONTROLLING THE INTERCONNECTION SYSTEM REPRESENTED BY THE CONFIGURATION CONTROL REGISTERS, WITH THE REDUNDANCY NECESSARY FOR RELIABLE ''''FAIL-SAFE'''' OPERATION OF THE SYSTEM, EACH OF A PLURALITY OF COMPUTING ELEMENTS IS PROVIDED WITH MEANS FOR INDEPENDENTY DEVELOPING, SELECTING AND CONDITIONING SIGNALS AND WITH MEANS FOR BROADCASTING THESE SIGNALS TO ALL ELEMENTS OF THE APPARATUS, INCLUDING THE ORIGINATING ELEMENT. THE SELECTING SIGNALS ARE ULTIZED AT THE RECEIVING ELEMENTS TO SELECTIVELY LIMIT APPLICATION OF THE CONDITIONING SIGNALS ONLY TO CONFIGURATION CONTROL REGISTERS OF ELEMENTS DESIGNATED BY THE SELECTING SIGNALS, SUCH ELEMENTS HAVING BEEN PREDETERMINED BY THE ORIGINATING COMPUTING ELEMENT. THE CONDITIONING SIGNALS SERVE TO CONDITION THE CONTROL REGISTERS OF THE SELECTED ELEMENTS TO DESIRED STATES OF INFORMATION FLOW CONTROL ALSO PREDETERMINED BY THE ORIGINATING COMPUTING ELEMENT.

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