Double gate transistor and method of fabricating the same

Claim 1

A double gate transistor, comprising: a semiconductor layer on a substrate; a fin structure formed in said semiconductor layer, said fin structure having two end portions for forming source and drain regions and a middle portion between said two end portions for forming a channel region, said middle portion including first and second parallel side surfaces perpendicular to a substrate surface; a first gate dielectric layer and a first gate disposed on the first side surface of said middle portion; and a second gate dielectric layer and a second gate disposed on the second side surface of said middle portion, characterized in that: said middle portion has a width larger than the width of the two end portions for forming source and drain regions, said middle portion has a length larger than the length of at least one of the first gate and the second gate, and a height of said first gate and a height of said second gate are both the same as a height of said middle portion, wherein the length runs along channel direction, the height runs along a direction perpendicular to the substrate surface, and the width runs along a direction perpendicular to the length and the height.

Claim 29

A method of fabricating a double gate transistor, comprising: providing a substrate with a semiconductor layer on its surface; forming a patterned hard mask on said semiconductor layer; etching said semiconductor layer with the hard mask to form a fin structure, said fin structure having two end portions for forming source and drain regions and a middle portion between said two end portions, side surfaces of said middle portion together with the respective adjacent side surfaces of said two end portions constituting two opposite side surfaces of said fin structure that are perpendicular to the substrate surface, wherein said middle portion has a width larger than the two end portions for forming source and drain regions; depositing gate dielectric and gate materials, so as to form a first stacked layer of the gate dielectric and gate materials on one side surface of said fin structure and a second stacked layer of the gate dielectric and gate materials on the other side surface of said fin structure, as well as to form a third stacked layer of the gate dielectric and gate materials on said hard mask; performing planarization by using said hard mask as a stop layer, so as to remove said third stacked layer and maintain said first stacked layer and said second stacked layer on the two opposite side surfaces of said fin structure, wherein the height of said first stacked layer and the height of said second stacked layer are both the same as the height of said middle portion; and selectively etching the gate dielectric and gate materials in said first stacked layer and said second stacked layer, so as to form a first gate dielectric layer and a second gate dielectric layer as well as a first gate and a second gate corresponding to said middle portion, and such that said middle portion has a length larger than at least one of the first gate and the second gate, wherein the length runs along channel direction, the height runs along a direction perpendicular to the substrate surface, and the width runs along a direction perpendicular to the length and the height respectively.

Claim 30

A method of fabricating a double gate transistor, comprising: providing a substrate with a semiconductor layer on its surface; forming a patterned hard mask on said semiconductor layer; etching said semiconductor layer with the hard mask to form a fin structure, said fin structure having two end portions for forming source and drain regions and a middle portion between said two end portions, side surfaces of said middle portion together with the respective adjacent side surfaces of said two end portions constituting two opposite side surfaces of said fin structure that are perpendicular to the substrate surface, wherein said middle portion has a width larger than the two end portions for forming source and drain regions; depositing gate dielectric and gate materials, so as to form a first stacked layer of the gate dielectric and gate materials on one side surface of said fin structure and a second stacked layer of the gate dielectric and gate materials on the other side surface of said fin structure, as well as to form a third stacked layer of the gate dielectric and gate materials on said hard mask; performing planarization by using said hard mask as a stop layer, so as to remove said third stacked layer and maintain said first stacked layer and said second stacked layer on the two opposite side surfaces of said fin structure, wherein the height of said first stacked layer and the height of said second stacked layer are both the same as the height of said middle portion; and selectively etching the gate dielectric and gate materials in said first stacked layer and said second stacked layer, so as to form a first gate dielectric layer and a second gate dielectric layer as well as a first gate and a second gate corresponding to said middle portion, and such that said middle portion has a length larger than at least one of the first gate and the second gate, wherein the length runs along channel direction, the height runs along a direction perpendicular to the substrate surface, and the width runs along a direction perpendicular to the length and the height respectively.