Multi-drop bus system

Claim 2

A memory system, comprising: a memory controller; first and second memory devices; and a signal line to couple the memory controller to the first and second memory devices, the signal line comprising: a first drop, having an associated first load impedance, to connect to the first memory device; a second drop, having an associated second load impedance, to connect to the second memory device; a first line segment, having a first characteristic impedance, to couple the controller to the first drop; and a second line segment, having a second characteristic impedance, to couple the first drop to the second drop, the second characteristic impedance being matched to the second load impedance.

Claim 3

The memory system of claim 1 , wherein the first and second load impedances and first and second characteristic impedances provide impedance matching on the signal line for signals transmitted from the memory controller.

Claim 4

The memory system of claim 2 , wherein the memory controller comprises a driver to transmit signals via the signal line, the driver having an associated impedance matched to the first characteristic impedance.

Claim 5

The memory system of claim 3 , wherein the first load impedance is 120 ohms, the second load impedance is 60 ohms, the first characteristic impedance is 40 ohms, the second characteristic impedance is 60 ohms, and the impedance associated with the driver is 40 ohms.

Claim 6

The memory system of claim 1 , wherein the first and second load impedances and first and second characteristic impedances provide imperfect impedance matching at the first drop for signals transmitted from the memory controller to the second memory device and from the second memory device to the memory controller.

Claim 7

The memory system of claim 1 , further comprising a circuit board, a first memory module, and a second memory module, wherein: the circuit board comprises the first and second line segments; the first memory device is situated on the first memory module; and the second memory device is situated on the second memory module.

Claim 8

The memory system of claim 6 , wherein: the first load impedance is an input impedance of the first memory module; and the second load impedance is an input impedance of the second memory module.

Claim 9

The memory system of claim 1 , wherein the second line segment comprises a micro-strip-line transmission line.

Claim 10

The memory system of claim 7 , wherein the first line segment comprises a micro-strip-line transmission line.

Claim 11

A memory system, comprising: a memory controller; multiple memory devices; and a multi-drop bus comprising one or more signal lines to couple the memory controller to the multiple memory devices, a respective signal line comprising: multiple drops, having associated load impedances, to connect to respective memory devices, the multiple drops comprising a first drop and an end-point drop; a first line segment, having a first characteristic impedance, to couple the memory controller to the first drop; and one or more additional line segments, having respective characteristic impedances, coupled between respective drops of the multiple drops, the one or more additional line segments comprising an end segment coupled to the end-point drop; wherein the characteristic impedance of the end segment is matched to the load impedance associated with the end-point drop.

Claim 12

A memory system, comprising: a memory controller; multiple memory devices; and a multi-drop bus comprising one or more signal lines to couple the memory controller to the multiple memory devices, a respective signal line comprising: multiple drops, having associated load impedances, to connect to respective memory devices, the multiple drops comprising a first drop and an end-point drop; a first line segment, having a first characteristic impedance, to couple the memory controller to the first drop; and one or more additional line segments, having respective characteristic impedances, coupled between respective drops of the multiple drops, the one or more additional line segments comprising an end segment coupled to the end-point drop; wherein the characteristic impedance of the end segment is matched to the load impedance associated with the end-point drop.

Claim 13

The memory system of claim 10 , wherein the load impedances and characteristic impedances provide impedance matching on the respective signal line for signals transmitted from the memory controller.

Claim 14

The memory system of claim 11 , wherein the memory controller comprises a driver to transmit signals via the respective signal line, the driver having an associated impedance matched to the first characteristic impedance.

Claim 15

The memory system of claim 12 , wherein: the one or more additional line segments consist of a second line segment and the end segment; the multiple drops consist of the first drop, a second drop, and the end-point drop; the load impedances of the first drop, second drop, and end-point drop are 120 ohms, 120 ohms, and 60 ohms, respectively; the characteristic impedances of the first line segment, second line segment, and end segment are 30 ohms, 40 ohms, and 60 ohms, respectively; and the impedance associated with the driver is 30 ohms.

Claim 16

The memory system of claim 10 , wherein the load impedances and characteristic impedances provide imperfect impedance matching at the first drop for signals transmitted from the memory controller to the end-point drop and from the end-point drop to the memory controller.

Claim 17

The memory system of claim 10 , further comprising a circuit board and multiple memory modules, wherein: the circuit board comprises the first line segment and the one or more additional line segments; respective subsets of the multiple memory devices are situated on respective memory modules of the multiple memory modules; and each of the multiple drops connects to a respective memory module of the multiple memory modules.

Claim 18

The memory system of claim 15 , wherein the load impedances are input impedances of respective memory modules of the multiple memory modules.

Claim 19

The memory system of claim 10 , wherein the end segment comprises a micro-strip-line transmission line.

Claim 20

The memory system of claim 17 , wherein: the one or more additional line segments further comprise an intermediate segment; and the first line segment and the intermediate segment each comprise a strip-line transmission line.

Claim 21

The memory system of claim 17 , wherein: the one or more additional line segments further comprise an intermediate segment; and the first line segment and the intermediate segment each comprise a micro-strip-line transmission line.

Claim 22

The memory system of claim 10 , wherein the one or more signal lines comprise multiple signal lines, each of the multiple signal lines comprising: multiple drops, having associated load impedances, to connect to respective memory devices, the multiple drops comprising a first drop and an end-point drop; a first line segment, having a first characteristic impedance, to couple the memory controller to the first drop; and one or more additional line segments, having respective characteristic impedances, coupled between respective drops of the multiple drops, the one or more additional line segments comprising an end segment coupled to the end-point drop, wherein the characteristic impedance of the end segment is matched to the load impedance associated with the end-point drop.