US6067594A
Expired / Lapsed
US
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High frequency bus system
Assignee: Rambus Inc
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Filing: 1997-09-26
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Granted: 2000-05-23
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Expires: 2017-09-26
Abstract
Abstract A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.
Inventors
- 👤 Donald V. Perino
- 👤 Billy Wayne Garrett, Jr.
- 👤 Haw-Jyh Liaw
- 👤 David Nguyen
- 👤 Srinivas Nimmagadda
- 👤 James A. Gasbarro
- 👤 Richard DeWitt Crisp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 05:44
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C5/063; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1684; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4086; G06F13/409; G06F13/42; G06F13/4247; G11C5/02; G11C5/04; H; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0237; H05K1/0246; H05K1/0248; H05K7/00; H05K7/14; H05K7/1438; H05K7/1459; G11C7/00; G11C7/10; G11C7/1048; H05K1/0216; H05K1/023; H05K1/14; H05K2201/00; H05K2201/04; H05K2201/044; H05K2201/09; H05K2201/09209; H05K2201/09218; H05K2201/09263; H05K2201/10; H05K2201/10007; H05K2201/10022; H05K2201/10159; H05K2201/10613; H05K2201/10621; H05K2201/10689
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
353 words
A high frequency bus system, comprising: a motherboard with a connection site linked to motherboard bus input lines and motherboard bus output lines; a module board positioned at said connection site, said module board including a first set of signal lines positioned on a first face of said module board, said first set of signal lines being connected to said mother board input lines, each signal line of said first set of signal lines including a first line segment, a first right angle turn node, and a second line segment at a right angle with respect to said first line segment, the linear length of said first line segment and said second line segment being selected for each signal line of said first set of signal lines to establish a fixed electrical length shared by each signal line of said first set of signal lines, said first set of signal lines thereby facilitating delivery to said motherboard bus output lines of output signals with a substantially uniform module board signal propagation delay; wherein said module board further includes a second set of signal lines connected to said bus output lines, each signal line of said second set of signal lines including a third line segment, a second right angle turn node, and a fourth line segment at a right angle with respect to said third line segment, the linear length of said third line segment and said fourth line segment being selected for each signal line of said second set of signal lines to establish a fixed electrical length shared by each signal line of said second set of signal lines; wherein said first right angle turn node and said second right angle turn node are each a via extending from an external module board surface to an internal module board location; and wherein said first line segment is positioned on an external module board surface of said module board, said second line segment and said third line segment are positioned internal to said module board, and said fourth line segment is positioned on an external module board surface of said module board.
Claim 2
Dependent Claim
353 words
A high frequency bus system, comprising: a motherboard with a connection site linked to motherboard bus input lines and motherboard bus output lines; a module board positioned at said connection site, said module board including a first set of signal lines positioned on a first face of said module board, said first set of signal lines being connected to said mother board input lines, each signal line of said first set of signal lines including a first line segment, a first right angle turn node, and a second line segment at a right angle with respect to said first line segment, the linear length of said first line segment and said second line segment being selected for each signal line of said first set of signal lines to establish a fixed electrical length shared by each signal line of said first set of signal lines, said first set of signal lines thereby facilitating delivery to said motherboard bus output lines of output signals with a substantially uniform module board signal propagation delay; wherein said module board further includes a second set of signal lines connected to said bus output lines, each signal line of said second set of signal lines including a third line segment, a second right angle turn node, and a fourth line segment at a right angle with respect to said third line segment, the linear length of said third line segment and said fourth line segment being selected for each signal line of said second set of signal lines to establish a fixed electrical length shared by each signal line of said second set of signal lines; wherein said first right angle turn node and said second right angle turn node are each a via extending from an external module board surface to an internal module board location; and wherein said first line segment is positioned on an external module board surface of said module board, said second line segment and said third line segment are positioned internal to said module board, and said fourth line segment is positioned on an external module board surface of said module board.
Claim 3
Dependent Claim
34 words
The high frequency bus system of claim 1 further comprising a plurality of memory devices positioned on said module board between said first set of signal lines and said second set of signal lines.
Claim 4
Dependent Claim
48 words
The high frequency bus system of claim 1 wherein said second line segment includes dual internal signal tracks with a loaded impedance corresponding to said first line segment, and said third line segment includes dual internal signal tracks with a loaded impedance corresponding to said fourth line segment.
Claim 5
Dependent Claim
17 words
The high frequency bus system of claim 1 further comprising a memory controller positioned on said motherboard.
Claim 6
Dependent Claim
17 words
The high frequency bus system of claim 4 further comprising a bus terminator positioned on said motherboard.
Claim 7
Dependent Claim
19 words
The high frequency bus system of claim 1 further comprising a plurality of module boards connected to said motherboard.
Claim 8
Dependent Claim
28 words
The high frequency bus system of claim 1 wherein said connection site includes through-holes positioned within said motherboard and said module board includes pins to engage said through-holes.
Claim 9
Dependent Claim
30 words
The high frequency bus system of claim 1 wherein said connection site includes a socket positioned on said motherboard and said module board includes edge fingers to engage said socket.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-23 | 2003-11-22 | 2004-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-23 | 2007-11-22 | 2008-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-23 | 2011-11-22 | 2012-05-23 | $7700.00 | Window Closed / Lapsed |