Controlling power supply in a multi-core processor

Claim 2

A power control apparatus for a multi-core processor, comprising: a processor including a first core and a second core; a first power conversion unit configured to independently supply a first supply voltage to the first core; a second power conversion unit configured to independently supply a second supply voltage to the second core; and a power management unit configured to receive information relating to a usage amount of each of the first and the second cores, the first supply voltage being controlled based on the information relating to the usage amount of the first core and being controlled independent of the information relating to the usage amount of the second core, and the second supply voltage being controlled based on the information relating to the usage amount of the second core and being controlled independent of the information relating to the usage amount of the first core, wherein the power management unit is operatively connected to an operating system.

Claim 3

The power control apparatus of claim 1 , wherein the first core is configured for supplying a voltage identification signal for the first power conversion unit, and the second core is configured for supplying a voltage identification signal for the second power conversion unit, wherein the voltage identification signal for the second core is different from the voltage identification signal for the first core.

Claim 4

The power control apparatus of claim 2 , wherein the first power conversion unit is configured for independently supplying the first supply voltage to the first core based upon the voltage identification signal from the first core.

Claim 5

The power control apparatus of claim 1 , wherein the first power conversion unit comprises a DC/DC converter connected to the first core and configured for applying a DC supply power to the first core.

Claim 6

The power control apparatus of claim 1 , wherein the first power conversion unit is configured for receiving a voltage identification signal from the first core and for adjusting a supply voltage to the first core to adjust an operating rate of the first core.

Claim 7

The power control apparatus of claim 1 , further comprising a plurality of frequency control devices for independently adjusting operating frequencies of the first and the second cores according to a usage amount for each of the first core and the second core.

Claim 8

The power control apparatus of claim 6 , wherein at least one of the frequency control devices comprises one or more phase locked loops.

Claim 9

The power control apparatus of claim 1 , wherein the first and second supply voltages are controlled based on a comparison of the information relating to the usage amount of the first and second cores to at least one threshold usage amount.

Claim 10

A power control method for a multi-core processor having multiple cores, the method comprising: obtaining information about a usage amount of each core; receiving an independent voltage identification signal for each core of the multi-core processor, each voltage identification signal being based on the information about the usage amount of a corresponding core and independent of the information about the usage amount of any other core; and independently supplying a supply voltage to each core of the multi-core processor based on the voltage identification signal for each core.

Claim 11

A power control method for a multi-core processor having multiple cores, the method comprising: obtaining information about a usage amount of each core; receiving an independent voltage identification signal for each core of the multi-core processor, each voltage identification signal being based on the information about the usage amount of a corresponding core and independent of the information about the usage amount of any other core; and independently supplying a supply voltage to each core of the multi-core processor based on the voltage identification signal for each core.

Claim 12

The method of claim 9 , further comprising: receiving a different voltage identification from each core; and independently adjusting the supply voltage for each core based on a usage amount of each core.

Claim 13

The method of claim 9 , wherein supplying the supply voltage to each core is based on a usage amount of each core.

Claim 14

The method of claim 9 , further comprising independently changing an operating frequency of each core.

Claim 15

The method of claim 9 , wherein supplying the supply voltage to each core comprises increasing the supply voltage to at least one core to increase an operating rate for the at least one core.

Claim 16

The method of claim 9 , wherein supplying the supply voltage to each core comprises decreasing the supply voltage to at least one core to decrease an operating rate for the at least one core.

Claim 17

The method of claim 9 , wherein each voltage identification signal is based on a comparison of the usage amount of the corresponding core to at least one threshold usage amount.

Claim 18

A power control apparatus for a multi-core processor, comprising: a multi-core processor including at least two cores, wherein the processor is configured to operate in two or more modes, each mode of the two or more modes having different operating rates; at least two power conversion units, each power conversion unit being operatively connected to one of the at least two cores for independently supplying a supply voltage to the connected core; and a power management unit configured to receive information relating to a usage amount of each of the at least two cores, and configured to control the supply voltage for each core based on the information relating to the usage amount of the cores respectively and being controlled independent of the information relating to the usage amount of another core, wherein the power management unit is operatively connected to an operating system; wherein each core of the at least two cores is configured for generating an independent voltage identification signal corresponding to each operating mode, and for transmitting the independent voltage identification signals to the power conversion units, and wherein each power conversion unit of the at least two power conversion units is configured for independently supplying the supply voltage to a respective core of the at least two cores based on the independent voltage identification signals.

Claim 19

A power control apparatus for a multi-core processor, comprising: a multi-core processor including at least two cores, wherein the processor is configured to operate in two or more modes, each mode of the two or more modes having different operating rates; at least two power conversion units, each power conversion unit being operatively connected to one of the at least two cores for independently supplying a supply voltage to the connected core; and a power management unit configured to receive information relating to a usage amount of each of the at least two cores, and configured to control the supply voltage for each core based on the information relating to the usage amount of the cores respectively and being controlled independent of the information relating to the usage amount of another core, wherein the power management unit is operatively connected to an operating system; wherein each core of the at least two cores is configured for generating an independent voltage identification signal corresponding to each operating mode, and for transmitting the independent voltage identification signals to the power conversion units, and wherein each power conversion unit of the at least two power conversion units is configured for independently supplying the supply voltage to a respective core of the at least two cores based on the independent voltage identification signals.

Claim 20

The power control apparatus of claim 16 , wherein the power conversion units each comprise a DC/DC converter for applying DC supply power.

Claim 21

The power control apparatus of claim 16 , wherein the supply voltage for each core is controlled based on a comparison of the information relating to the usage amount of the cores to at least one threshold usage amount.

Claim 22

A computer-readable recording medium having computer-executable program instructions embodied thereon for performing a power control method for a multi-core processor, the method comprising: obtaining information about a usage amount of each core, wherein the information about a usage amount of each core includes information obtained from an operating system; receiving a voltage identification signal for each core of the multi-core processor each voltage identification signal being based on the information about the usage amount of a corresponding core independent of the information about the usage amount of another core; and independently supplying a supply voltage to the corresponding core of the multi-core processor based on the voltage identification signal for each of the cores.

Claim 23

A computer-readable recording medium having computer-executable program instructions embodied thereon for performing a power control method for a multi-core processor, the method comprising: obtaining information about a usage amount of each core, wherein the information about a usage amount of each core includes information obtained from an operating system; receiving a voltage identification signal for each core of the multi-core processor each voltage identification signal being based on the information about the usage amount of a corresponding core independent of the information about the usage amount of another core; and independently supplying a supply voltage to the corresponding core of the multi-core processor based on the voltage identification signal for each of the cores.

Claim 24

The computer-readable recording medium claim 19 , wherein each voltage identification signal is based on a comparison of the information about the usage amount of each core to at least one threshold usage amount.