Data output strobe signal generating circuit and semiconductor memory apparatus having the same

Claim 2

A data output strobe signal generating circuit comprising: a duty cycle correcting unit configured to correct a duty cycle of an input clock in response to a control signal, thereby outputting a corrected clock; a data output strobe signal generating unit configured to receive the corrected clock, thereby generating a data output strobe signal; and a duty cycle control unit configured to receive the data output strobe signal, thereby outputting the control signal, wherein the duty cycle control unit includes a feedback loop to generate a feedback signal by delaying the data output strobe signal, determine a duty ratio of the data output strobe signal using the feedback signal comparing a phase of the data output strobe signal with a phase of the feedback signal, and increases/decreases logical values of a plurality of signals based on the duty ratio to output the plurality of the signals as the control signal.

Claim 3

The data output strobe signal generating circuit of claim 1 , wherein the duty cycle correcting unit is configured to correct the duty cycle of the input clock according to a number of high-level signals and a number of low-level signals included in the control signal.

Claim 4

The data output strobe signal generating circuit of claim 2 , wherein the duty cycle correcting unit comprises: a pull-up unit configured to control an external power supply voltage in response to the control signal; a pull-down unit configured to control a ground power supply voltage in response to the control signal; and a driving unit configured to receive the voltage from the pull-up unit and the pull-down unit and to drive the input clock based thereon, thereby outputting the corrected clock.

Claim 5

The data output strobe signal generating circuit of claim 3 , wherein the pull-up unit comprises a plurality of transistors connected in parallel to each other between an external power supply voltage terminal and the driving unit; and wherein each of the transistors has a gate which receives a respective one of the signals included in the control signal.

Claim 6

The data output strobe signal generating circuit of claim 3 , wherein the pull-down unit comprises a plurality of transistors connected in parallel to each other between a ground power supply voltage terminal and the driving unit; and wherein each of the transistors has a gate which receives a respective one of the signals included in the control signal.

Claim 7

The data output strobe signal generating circuit of claim 3 , wherein the driving unit comprises: a first inverter that is supplied with the voltage from the pull-up unit and the pull-down unit and receives the input clock to provide an output signal; and a second inverter that receives the output signal of the first inverter and outputs the corrected clock.

Claim 8

The data output strobe signal generating circuit of claim 1 , wherein the duty cycle control unit comprises: a phase comparing unit configured to compare a phase of the data output strobe signal with a phase of the feedback signal to generate a phase comparison signal; a delay control unit configured to generate a delay control signal in response to the phase comparison signal; a delay unit configured to delay the data output strobe signal by a time corresponding to the delay control signal to obtain a delayed signal and to invert the delayed signal, to generate the feedback signal; a duty detecting unit configured to invert the data output strobe signal and the feedback signal to obtain inverted signals and to compare the phases of the inverted signals to generate a counting enable signal; and a counter configured to generate the control signal in response to the counting enable signal.

Claim 9

The data output strobe signal generating circuit of claim 7 , wherein the phase comparing unit is configured to output the phase comparison signal including information on rising edge timings of the data output strobe signal and the feedback signal.

Claim 10

The data output strobe signal generating circuit of claim 7 , wherein the duty detecting unit is configured to compare rising edges of the inverted signals and to enable the counting enable signal according to a result of the comparison.

Claim 11

The data output strobe signal generating circuit of claim 7 , wherein, when the counting enable signal is enabled, the counter is configured to change a number of high-level signals included in the control signal.

Claim 12

A semiconductor memory apparatus comprising: a DLL circuit configured to generate a DLL clock having a phase which leads a phase of an external clock by a predetermined amount of time in order to compensate for a delay of a clock by internal delay elements provided in the semiconductor memory apparatus; a transmission line configured to transmit the DLL clock; a data output strobe signal generating circuit configured to correct a duty cycle of the DLL clock transmitted through the transmission line to obtain a corrected clock, thereby generating a data output strobe signal using the corrected clock; and a data output buffer configured to receive the data output strobe signal, thereby buffering output data wherein the data output strobe signal generating circuit comprises: a phase splitter configured to divide the DLL clock to generate a rising clock and a falling clock; a first duty cycle correcting unit configured to correct a duty ratio of the rising clock in response to a control signal to output a corrected rising clock; a second duty cycle correcting unit configured to correct a duty ratio of the falling clock in response to the control signal to output a corrected falling clock; a data output strobe signal generating unit configured to receive the corrected rising clock and the corrected falling clock, thereby generating the data output strobe signal; and a duty cycle control unit configured to receive the data output strobe signal, thereby outputting the control signal.

Claim 13

A semiconductor memory apparatus comprising: a DLL circuit configured to generate a DLL clock having a phase which leads a phase of an external clock by a predetermined amount of time in order to compensate for a delay of a clock by internal delay elements provided in the semiconductor memory apparatus; a transmission line configured to transmit the DLL clock; a data output strobe signal generating circuit configured to correct a duty cycle of the DLL clock transmitted through the transmission line to obtain a corrected clock, thereby generating a data output strobe signal using the corrected clock; and a data output buffer configured to receive the data output strobe signal, thereby buffering output data wherein the data output strobe signal generating circuit comprises: a phase splitter configured to divide the DLL clock to generate a rising clock and a falling clock; a first duty cycle correcting unit configured to correct a duty ratio of the rising clock in response to a control signal to output a corrected rising clock; a second duty cycle correcting unit configured to correct a duty ratio of the falling clock in response to the control signal to output a corrected falling clock; a data output strobe signal generating unit configured to receive the corrected rising clock and the corrected falling clock, thereby generating the data output strobe signal; and a duty cycle control unit configured to receive the data output strobe signal, thereby outputting the control signal.

Claim 14

The semiconductor memory apparatus of claim 11 , wherein the control signal is composed of a combination of a plurality of signals, and the first and second duty cycle correcting units are configured to correct the duty ratios of the rising clock and the falling clock according to a number of high-level signals and a number of low-level signals included in the control signal, respectively.

Claim 15

The semiconductor memory apparatus of claim 12 , wherein the first duty cycle correcting unit comprises: a pull-up unit configured to control an external power supply voltage in response to the control signal; a pull-down unit configured to control a ground power supply voltage in response to the control signal; and a driving unit configured to receive the voltage from the pull-up unit and the pull-down unit and to drive the rising clock, thereby outputting the corrected rising clock.

Claim 16

The semiconductor memory apparatus of claim 12 , wherein the second duty cycle correcting unit comprises: a pull-up unit configured to control an external power supply voltage in response to the control signal; a pull-down unit configured to control the supply of a ground power supply voltage in response to an inverted signal of the control signal; and a driving unit configured to receive the voltage from the pull-up unit and the pull-down unit and to drive the falling clock, thereby outputting the corrected falling clock.

Claim 17

The semiconductor memory apparatus of claim 11 , wherein the duty cycle control unit comprises a feedback loop to determine a duty ratio of the data output strobe signal, and increases/decreases logical values of a plurality of signals on the basis of a result of the determination to generate the control signal.

Claim 18

The semiconductor memory apparatus of claim 11 , wherein the duty cycle control unit comprises: a phase comparing unit configured to compare a phase of the data output strobe signal with a phase of a feedback signal to generate a phase comparison signal; a delay control unit configured to generate a delay control signal in response to the phase comparison signal; a delay unit configured to delay the data output strobe signal by a time corresponding to the delay control signal to obtain a delayed signal and to invert the delayed signal to generate the feedback signal; a duty detecting unit configured to invert the data output strobe signal and the feedback signal to obtain inverted signals and to compare the phases of the inverted signals to generate a counting enable signal; and a counter configured to generate the control signal in response to the counting enable signal.

Claim 21

The method of claim 17 , wherein the generating of the corrected clock corrects the duty ratio of the input clock according to a number of high-level signals and a number of low-level signals included in the control signal.

Claim 22

The method of claim 17 , wherein the outputting of the control signal comprises: comparing a phase of the data output strobe signal with a phase of the feedback signal to generate a phase comparison signal; generating a delay control signal in response to the phase comparison signal; delaying the data output strobe signal by a time corresponding to the delay control signal to obtain a delayed signal, and inverting the delayed signal to generate the feedback signal; inverting the data output strobe signal and the feedback signal to obtain inverted signals and comparing phases of the inverted signals to generate a counting enable signal; and generating the control signal in response to the counting enable signal.

Claim 23

The method of claim 19 , wherein the comparing of the phases outputs the phase comparison signal including information on rising edge timings of the data output strobe signal and the feedback signal.

Claim 24

The method of claim 19 , wherein the generating of the counting enable signal comprises: comparing rising edges of the inverted signals; and enabling the counting enable signal according to a result of the comparison.

Claim 25

The method of claim 19 , wherein, when the counting enable signal is enabled, the generating of the control signal changes a number of high-level signals included in the control signal.

Claim 28

The method of claim 23 , wherein the control signal is composed of a combination of a plurality of signals, and wherein the generating of the corrected rising clock and the corrected falling clock corrects the duty ratios of the rising clock and the falling clock according to a number of high-level signals and a number of low-level signals included in the control signal, respectively.

Claim 29

The method of claim 24 , wherein the outputting of the control signal includes determining a duty ratio of the data output strobe signal using a feedback loop, and increasing/decreasing logical values of the plurality of signals on the basis of a result of the determination to generate the control signal.

Claim 30

The method of claim 23 , wherein the outputting of the control signal comprises: comparing a phase of the data output strobe signal with a phase of a feedback signal to generate a phase comparison signal; generating a delay control signal in response to the phase comparison signal; delaying the data output strobe signal by a time corresponding to the delay control signal to obtain a delayed signal, and inverting the delayed signal to generate the feedback signal; inverting the data output strobe signal and the feedback signal to obtain inverted signals and comparing phases of the inverted signals to generate a counting enable signal; and generating the control signal in response to the counting enable signal.

Claim 31

The method of claim 26 , wherein the comparing of the phases includes outputting the phase comparison signal including information on rising edge timings of the data output strobe signal and the feedback signal.

Claim 32

The method of claim 26 , wherein the generating of the counting enable signal comprises: comparing rising edges of the inverted signals; and enabling the counting enable signal according to a result of the comparison.

Claim 33

The method of claim 26 , wherein, when the counting enable signal is enabled, the generating of the control signal changes a number of high-level signals included in the control signal.