Patent US7583985B2 successfully refreshed from Google Patents.
US7583985B2
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MAC controlled sleep mode/wake-up mode with staged wake-up for power management
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 2004-03-26
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Granted: 2009-09-01
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Expires: 2024-03-26
Abstract
Abstract A power management scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By incorporating controls for sleep and wake-up mode transitions in the processor's control logic, improved power savings with reduced latency is provided, obviating the need for hardware-focused solutions with elaborate signaling mechanisms. A fully integrated power management with staged wake-up operations controlled by the MAC solution consumes less power than the conventional wireless LAN solutions in standby mode.
Inventors
- 👤 Mark D. Matson
- 👤 Bruce E. Edwards
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:57
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3209; H; H04; H04B; H04B1/00; H04B1/06; H04B1/16; H04B1/1607; H04B1/1615; H04W; H04W52/00; H04W52/02; H04W52/0209; H04W52/0225; H04W52/0229; H04W52/0235; Y; Y02; Y02D; Y02D30/00; Y02D30/70
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
92 words
A data processor for use in a wireless communication device, comprising: a processing unit; an instruction pipeline circuit; at least one processing module; a timer for generating a time-out interval; and power control logic for detecting a sleep instruction and placing the processing unit, instruction pipeline circuit and at least one processing module in a low-power state, where the power control logic is operative in response to a wake-up signal to reactivate the instruction pipeline circuit, and consequently at least one processing module only to the extent required by the wake-up signal.
Claim 2
Dependent Claim
92 words
A data processor for use in a wireless communication device, comprising: a processing unit; an instruction pipeline circuit; at least one processing module; a timer for generating a time-out interval; and power control logic for detecting a sleep instruction and placing the processing unit, instruction pipeline circuit and at least one processing module in a low-power state, where the power control logic is operative in response to a wake-up signal to reactivate the instruction pipeline circuit, and consequently at least one processing module only to the extent required by the wake-up signal.
Claim 3
Dependent Claim
17 words
The processor of claim 1 , where the instruction pipeline circuit comprises a multi-stage instruction pipeline circuit.
Claim 4
Dependent Claim
26 words
The processor of claim 1 , where the wake-up signal comprises a logical OR combination of one or more predetermined wake-up conditions and the time-out interval.
Claim 5
Dependent Claim
20 words
The processor of claim 1 , where the power control logic comprises instruction decode logic to detect the sleep instruction.
Claim 6
Dependent Claim
21 words
The processor of claim 1 , where the power control logic comprises branch condition logic to respond to the wake-up signal.
Claim 7
Dependent Claim
46 words
The processor of claim 1 , where the power control logic, having specified one or more wake-up conditions that the processing unit will respond to when in a low-power state, generates the wake-up signal upon detecting the one or more wake-up conditions or the time-out interval.
Claim 8
Dependent Claim
24 words
The processor of claim 1 , where the power control logic instructs the instruction pipeline circuit to complete any instructions preceding the sleep instruction.
Claim 9
Dependent Claim
32 words
The processor of claim 7 , where the power control logic instructs the instruction pipeline circuit to cease fetching new instructions after encountering a sleep instruction whose wake-up conditions are currently deasserted.
Claim 10
Dependent Claim
30 words
The processor of claim 1 , wherein the processing unit, instruction pipeline circuit and at least one processing module are formed together on a common silicon substrate using CMOS processing.
Claim 11
Dependent Claim
23 words
The processor of claim 6 , wherein the wake-up conditions and time-out interval are stored in a register by the power control logic.
Claim 12
Dependent Claim
115 words
An article of manufacture having at least one computer readable medium encoded with a computer program comprising executable instructions and data which, when executed by at least one processing device, cause the at least one processing device to: detect a sleep instruction for the processing device; specify one or more wake-up conditions and a time-out interval; power down an instruction pipeline and one or more processor modules; reactivate the instruction pipeline upon detection of a wake-up signal corresponding to either a wake-up condition or the time-out interval, and process one or more instructions in the instruction pipeline to reactivate any of the one or more processor modules required to respond to a detected wake-up condition.
Claim 13
Dependent Claim
115 words
An article of manufacture having at least one computer readable medium encoded with a computer program comprising executable instructions and data which, when executed by at least one processing device, cause the at least one processing device to: detect a sleep instruction for the processing device; specify one or more wake-up conditions and a time-out interval; power down an instruction pipeline and one or more processor modules; reactivate the instruction pipeline upon detection of a wake-up signal corresponding to either a wake-up condition or the time-out interval, and process one or more instructions in the instruction pipeline to reactivate any of the one or more processor modules required to respond to a detected wake-up condition.
Claim 14
Dependent Claim
26 words
The article of manufacture of claim 11 , wherein the processing device executes any instructions received by the instruction pipeline before the sleep instruction is received.
Claim 15
Dependent Claim
49 words
The article of manufacture of claim 11 , wherein the instruction pipeline comprises a multistage instruction pipeline, and the processing device reactivates only stages in the multistage instruction pipeline and/or the function units needed to process one or more instructions necessary to analyze and respond to the wake-up signal.
Claim 16
Dependent Claim
22 words
The article of manufacture of claim 11 , further comprising a register for holding the specified wake-up conditions and time out signal.
Claim 17
Dependent Claim
22 words
The article of manufacture of claim 11 , where the processing device is implemented as part of a single-chip wireless communication device.
Claim 18
Dependent Claim
25 words
The article of manufacture of claim 11 , where the executable instructions and data comprise control logic for controlling the operation of the processing device.
Claim 19
Dependent Claim
31 words
The article of manufacture of claim 11 , where the processing device powers down the one or more processor modules by freezing a clock signal for said one or more modules.
Claim 20
Dependent Claim
31 words
The article of manufacture of claim 11 , where the processing device powers down the one or more processor modules by placing said one or more modules in an idle mode.
Claim 21
Independent Claim
102 words
A method for managing power in a communications processor by selectively removing one or more processor modules from a standby mode, comprising: storing one or more wake-up conditions and a time-out interval in a register; receiving a processor sleep instruction; executing any pending instructions received by the processor before the sleep instruction; powering down the one or more processor modules, where one of the processor modules comprises an instruction pipeline circuit; receiving a processor wake-up signal corresponding to one of said wake-up conditions or said time-out interval; powering up only the processor modules required to respond to the detected processor wake-up signal.
Claim 22
Independent Claim
102 words
A method for managing power in a communications processor by selectively removing one or more processor modules from a standby mode, comprising: storing one or more wake-up conditions and a time-out interval in a register; receiving a processor sleep instruction; executing any pending instructions received by the processor before the sleep instruction; powering down the one or more processor modules, where one of the processor modules comprises an instruction pipeline circuit; receiving a processor wake-up signal corresponding to one of said wake-up conditions or said time-out interval; powering up only the processor modules required to respond to the detected processor wake-up signal.
Claim 23
Dependent Claim
20 words
The method of claim 19 , wherein one of the instruction pipeline circuit comprises a plurality of instruction pipeline stages.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2012-08-31 | 2013-03-02 | 2013-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2016-08-31 | 2017-03-02 | 2017-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2020-08-31 | 2021-03-02 | 2021-09-01 | $7700.00 | Window Closed / Lapsed |