Patent US7368993B2 successfully refreshed from Google Patents.
US7368993B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transconductance circuit with improved linearity
Assignee: MediaTek Inc
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Filing: 2006-02-10
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Granted: 2008-05-06
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Expires: 2026-02-10
Abstract
Abstract A transconductance circuit, comprising: first and second field effect transistors, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gate of the first and second transistors are connected to receive an input signal; and wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor.
Inventors
- 👤 Federico Alessandro Fabrizio Beffa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:44
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/32; H03F1/3205; H03F1/08; H03F1/22; H03F1/223
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
142 words
A transconductance circuit, comprising: first and second field effect transistors of a same type, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gates of the first and second transistors are connected to receive an input signal; and wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor.
Claim 2
Dependent Claim
142 words
A transconductance circuit, comprising: first and second field effect transistors of a same type, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gates of the first and second transistors are connected to receive an input signal; and wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor.
Claim 3
Dependent Claim
28 words
A transconductance circuit as claimed in claim 1 , in which the voltage modulator comprises a third field effect transistor in series with the second field effect transistors.
Claim 4
Dependent Claim
26 words
A transconductance circuit as claimed in claim 1 , in which the gate of the first field effect transistor is connected to a first bias node.
Claim 5
Dependent Claim
26 words
A transconductance circuit as claimed in claim 1 , in which the gate of the second field effect transistor is connected to a second bias node.
Claim 6
Dependent Claim
24 words
A transconductance circuit as claimed in claim 2 , in which the gate of the third transistor is connected to a third bias node.
Claim 7
Dependent Claim
41 words
A transconductance circuit as claimed in claim 1 , in which the modulator comprises a third field effect transistor in series with the second field effect transistor and the gate of the third transistor is connected to the second bias node.
Claim 8
Dependent Claim
52 words
A transconductance circuit as claimed in claim 1 , in which a fourth transistor is interposed between the first transistor and the second node, the drain of the first transistor is connected to the source of the fourth transistor and the drain of the fourth transistor is connected to the second node.
Claim 9
Dependent Claim
24 words
A transconductance circuit as claimed in claim 7 , in which the gate of the fourth transistor is connected to a fourth bias node.
Claim 10
Dependent Claim
42 words
A transconductance circuit as claimed in claim 2 , in which the source of the third transistor is connected to the drain of the second transistor and the drain of the third transistor is connected to the second node of the amplifier.
Claim 11
Dependent Claim
56 words
A transconductance circuit as claimed in claim 1 , in which the first and second transistors are biased such that over an operating range changes in transconductance of the first transistor with respect to changes in gate-source voltage are in opposition to changes in transconductance of the second transistor with respect to changes in gate-source voltage.
Claim 12
Dependent Claim
17 words
A transconductance circuit as claimed in claim 1 , in which the voltage modulator is a resistor.
Claim 13
Dependent Claim
20 words
A transconductance circuit as claimed in claim 11 , in which the resistor is in series with a cascode transistor.
Claim 14
Dependent Claim
24 words
A transconductance circuit as claimed in claim 10 , in which the operating range covers an AC signal input range of substantially ±100 mV.
Claim 15
Dependent Claim
19 words
A transconductance circuit as claimed in claim 10 , in which the operating signal range is substantially ±330 mV.
Claim 16
Dependent Claim
49 words
A transconductance circuit as claimed in claim 1 , in combination with a bias circuit, wherein the bias circuit includes a derivative calculator for calculating the derivative of the transconductance and a feedback circuit for adjusting a bias voltage as a function of the calculated derivative of the transconductance.
Claim 17
Independent Claim
119 words
A method of compensating for non-linearities of a first field effect transistor, where the first transistor is operated as a single-ended amplifier and is, in use, biased into its saturation region of its transfer characteristic, the method comprising the steps of providing a second field effect transistor in parallel with the first transistor and of a same type as the first field effect transistor, the second transistor being biased into its “linear region” and in series with a modulator for modulating its drain-source voltage as a function of an input signal to the first field effect transistor such that changes in its transconductance with respect to input voltage partially or wholly cancel changes in transconductance of the first transistor.
Claim 18
Independent Claim
119 words
A method of compensating for non-linearities of a first field effect transistor, where the first transistor is operated as a single-ended amplifier and is, in use, biased into its saturation region of its transfer characteristic, the method comprising the steps of providing a second field effect transistor in parallel with the first transistor and of a same type as the first field effect transistor, the second transistor being biased into its “linear region” and in series with a modulator for modulating its drain-source voltage as a function of an input signal to the first field effect transistor such that changes in its transconductance with respect to input voltage partially or wholly cancel changes in transconductance of the first transistor.
Claim 19
Dependent Claim
42 words
A method as claimed in claim 16 , wherein the modulator is a further field effect transistor in series with the second field effect transistor having its gate held at a constant voltage with respect to the source of the first transistor.
Claim 20
Dependent Claim
140 words
A single ended transconductance circuit, comprising: first and second field effect transistors, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gates of the first and second transistors are connected to receive an input signal; and wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor.
Claim 21
Dependent Claim
140 words
A single ended transconductance circuit, comprising: first and second field effect transistors, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gates of the first and second transistors are connected to receive an input signal; and wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor.
Claim 22
Dependent Claim
22 words
A transconductance circuit as claimed in claim 18 , in which the first and second field effect transistors are N type devices.
Claim 23
Dependent Claim
21 words
A transconductance circuit as claimed in claim 18 , in which the first and second current flow paths are in parallel.
Claim 24
Dependent Claim
28 words
A transconductance circuit as claimed in claim 18 , in which the voltage modulator comprises a third field effect transistor in series with the second field effect transistors.
Claim 25
Dependent Claim
52 words
A transconductance circuit as claimed in claim 21 , in which a fourth transistor is interposed between the first transistor and the second node, the drain of the first transistor is connected to the source of the fourth transistor and the drain of the fourth transistor is connected to the second node.
Claim 26
Dependent Claim
56 words
A transconductance circuit as claimed in claim 18 , in which the first and second transistors are biased such that over an operating range changes in transconductance of the first transistor with respect to changes in gate-source voltage are in opposition to changes in transconductance of the second transistor with respect to changes in gate-source voltage.
Claim 27
Dependent Claim
182 words
A transconductance circuit, comprising: first and second field effect transistors, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gates of the first and second transistors are connected to receive an input signal; and wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor, and in which a further transistor is interposed between the first transistor and the second node, the drain of the first transistor is connected to the source of the further transistor and the drain of the further transistor is connected to the second node.
Claim 28
Dependent Claim
182 words
A transconductance circuit, comprising: first and second field effect transistors, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gates of the first and second transistors are connected to receive an input signal; and wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor, and in which a further transistor is interposed between the first transistor and the second node, the drain of the first transistor is connected to the source of the further transistor and the drain of the further transistor is connected to the second node.
Claim 29
Dependent Claim
24 words
A transconductance circuit as claimed in claim 24 , in which the gate of the further transistor is connected to a fourth bias node.
Claim 30
Dependent Claim
186 words
A transconductance circuit, comprising: first and second field effect transistors, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gates of the first and second transistors are connected to receive an input signal; and wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor, and in which the first and second transistors are biased such that over an operating range changes in transconductance of the first transistor with respect to changes in gate-source voltage are in opposition to changes in transconductance of the second transistor with respect to changes in gate-source voltage.
Claim 31
Dependent Claim
186 words
A transconductance circuit, comprising: first and second field effect transistors, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gates of the first and second transistors are connected to receive an input signal; and wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor, and in which the first and second transistors are biased such that over an operating range changes in transconductance of the first transistor with respect to changes in gate-source voltage are in opposition to changes in transconductance of the second transistor with respect to changes in gate-source voltage.
Claim 32
Dependent Claim
153 words
A transconductance circuit, comprising: first and second field effect transistors, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gates of the first and second transistors are connected to receive an input signal; and wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor, and in which the voltage modulator is a resistor in series with a cascode transistor.
Claim 33
Dependent Claim
153 words
A transconductance circuit, comprising: first and second field effect transistors, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gates of the first and second transistors are connected to receive an input signal; and wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor, and in which the voltage modulator is a resistor in series with a cascode transistor.
Claim 34
Dependent Claim
178 words
A transconductance circuit, comprising: first and second field effect transistors, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gates of the first and second transistors are connected to receive an input signal; wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor; and in combination with a bias circuit, wherein the bias circuit includes a derivative calculator for calculating the derivative of the transconductance and a feedback circuit for adjusting a bias voltage as a function of the calculated derivative of the transconductance.
Claim 35
Dependent Claim
178 words
A transconductance circuit, comprising: first and second field effect transistors, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gates of the first and second transistors are connected to receive an input signal; wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor; and in combination with a bias circuit, wherein the bias circuit includes a derivative calculator for calculating the derivative of the transconductance and a feedback circuit for adjusting a bias voltage as a function of the calculated derivative of the transconductance.
References Cited (Backward Citations)
US6396311B2
Cited
US20060097788A1
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 7.5 Years (Year 8) | 2015-05-06 | 2015-11-05 | 2016-05-06 | $3760.00 | Window Closed / Lapsed |
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