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US7358551B2
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Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions
Assignee: GlobalFoundries US Inc
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Filing: 2005-07-21
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Granted: 2008-04-15
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Expires: 2025-07-21
Abstract
Abstract The present invention provides a technique for forming a CMOS structure including at least one pFET that has a stressed channel which avoids the problems mentioned in the prior art. Specifically, the present invention provides a method for avoiding formation of deep canyons at the interface between the active area and the trench isolation region, without requiring a trench isolation pulldown, thereby eliminating the problems of silicide to source/drain shorts and contact issues. At the same time, the method of the present invention provides a structure that allows for a facet to form at the spacer edge, retaining the Miller capacitance benefit that such a structure provides. The inventive structure also results in higher uniaxial stress in the MOSFET channel compared to one which allows for a facet to grow at the trench isolation edge.
Inventors
- 👤 Dureseti Chidambarrao
- 👤 Brian J. Greene
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:32
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/791; H10D30/797; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/013; H10D84/0133; H10D84/0165; H10D84/0167; H10D84/017; H10D84/02; H10D84/03; H10D84/038; H10D30/01; H10D30/021; H10D30/0212; H10D30/027; H10D30/0275; H10D62/00; H10D62/01; H10D62/021; H10D62/80; H10D62/82; H10D62/822
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
150 words
A semiconductor structure comprising: a semiconductor substrate including at least one trench isolation region embedded therein, said at least one trench isolation region comprises an inner trench dielectric, a nitride lining said inner trench dielectric and an oxide lining a portion of said nitride, wherein said oxide is not located at an upper surface of said inner trench dielectric and said nitride; at least one gate region located on a surface of said semiconductor substrate, said at least one gate region including at least a gate dielectric, gate conductor and an inner oxide spacer having a notched lower surface; and a stress inducing material embedded within said semiconductor substrate at a footprint of said at least one gate region, said stress inducing material has a faceted surface at the notched lower surface, but does not have a faceted surface at an edge of said at least one trench isolation region.
Claim 2
Dependent Claim
150 words
A semiconductor structure comprising: a semiconductor substrate including at least one trench isolation region embedded therein, said at least one trench isolation region comprises an inner trench dielectric, a nitride lining said inner trench dielectric and an oxide lining a portion of said nitride, wherein said oxide is not located at an upper surface of said inner trench dielectric and said nitride; at least one gate region located on a surface of said semiconductor substrate, said at least one gate region including at least a gate dielectric, gate conductor and an inner oxide spacer having a notched lower surface; and a stress inducing material embedded within said semiconductor substrate at a footprint of said at least one gate region, said stress inducing material has a faceted surface at the notched lower surface, but does not have a faceted surface at an edge of said at least one trench isolation region.
Claim 3
Dependent Claim
37 words
The semiconductor structure of claim 1 wherein said semiconductor substrate comprises one of Si, Ge, SiC, SiGeC, Ge, GaAs, InAs, GaN, InP, a layered semiconductor, or a hybrid oriented substrate having planar surfaces of different crystal orientation.
Claim 4
Dependent Claim
16 words
The semiconductor structure of claim 1 wherein said gate region is a p-type field effect transistor.
Claim 5
Dependent Claim
17 words
The semiconductor structure of claim 1 further comprising an outer spacer located on said inner oxide spacer.
Claim 6
Dependent Claim
34 words
The semiconductor structure of claim 1 wherein said oxide liner has a thickness from about 2 to about 25 nm, and said nitride liner has a thickness from about 10 to about 50 nm.
Claim 7
Dependent Claim
23 words
The semiconductor structure of claim 1 wherein said gate dielectric comprises one of an oxide, a metal oxide or a mixed metal oxide.
Claim 8
Dependent Claim
38 words
The semiconductor structure of claim 1 wherein said gate conductor comprises one of a Si-containing material, an elemental metal, an alloy of an element metal, a nitride of an elemental metal or a silicide of an elemental metal.
Claim 9
Dependent Claim
21 words
The semiconductor structure of claim 1 wherein said stress inducing material comprises an alloy of Si and Ge, and optionally C.
Claim 10
Dependent Claim
15 words
The semiconductor structure of claim 1 further comprising a silicide on said stress inducing material.
Claim 11
Dependent Claim
21 words
The semiconductor structure of claim 9 wherein said silicide includes a silicide of Ni, Co, Ti, Pt, W, or their alloys.
Claim 12
Dependent Claim
16 words
The semiconductor structure of claim 1 further comprising a stress inducing liner about the gate region.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 7.5 Years (Year 8) | 2015-04-15 | 2015-10-15 | 2016-04-15 | $3760.00 | Window Closed / Lapsed |
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