Method and circuit for deciding data transfer rate

Claim 2

A data transfer rate deciding method, comprising: identifying a data transfer rate in a procedure performed before data transfer; separating data and a clock pulse from a received signal upon reception of the data transfer; generating a first signal from the clock pulse, the first signal being synchronized with a reference frequency clock pulse based on the data transfer rate identified in the procedure; generating a second signal from the first signal, the second signal being synchronized with the reference frequency clock pulse based on the data transfer rate identified in the procedure; outputting a signal for notifying whether or not the data transfer rate identified in the procedure and a data transfer rate of received data differ based on whether or not a value of an exclusive-NOR of the first signal and the second signal is maintained as a low level; and detecting that the low level is not maintained and outputting an error notification signal, responsive to said outputting a signal.

Claim 3

The data transfer rate deciding method of claim 1 , wherein the reference frequency clock pulse is replaced with a signal that is a logical AND of an inversion signal and the reference frequency clock pulse, wherein the inversion signal corresponds to the error notification signal inverted.

Claim 4

The data transfer rate deciding method of claim 1 , wherein in the event that the error notification signal is output in excess of a prescribed number of times, an excess notification signal indicative thereof is provided.

Claim 5

The data transfer rate deciding method of claim 3 , wherein the prescribed number of times is set arbitrarily.

Claim 6

A data transfer rate deciding method, comprising: separating data and a clock pulse from a received signal upon reception of a data transfer; generating first signals from the clock pulse, the first signals being respectively synchronized with reference frequency clock pulses of predetermined different frequencies; generating respective second signals responsive to the first signals; determining respective exclusive-NOR values of each of the first signals as taken with respect to the respective second signals; detecting whether or not the respective exclusive-NOR values are maintained at low levels, and outputting responsive thereto respective detection signals indicative of whether or not a data transfer rate of the received signal respectively differs from the data transfer rates corresponding to the reference frequency clock pulses; and generating error notification signals for each of the reference frequency clock pulses when the low levels are not maintained, responsive to the detection signals.

Claim 7

A data transfer rate deciding method, comprising: separating data and a clock pulse from a received signal upon reception of a data transfer; generating first signals from the clock pulse, the first signals being respectively synchronized with reference frequency clock pulses of predetermined different frequencies; generating respective second signals responsive to the first signals; determining respective exclusive-NOR values of each of the first signals as taken with respect to the respective second signals; detecting whether or not the respective exclusive-NOR values are maintained at low levels, and outputting responsive thereto respective detection signals indicative of whether or not a data transfer rate of the received signal respectively differs from the data transfer rates corresponding to the reference frequency clock pulses; and generating error notification signals for each of the reference frequency clock pulses when the low levels are not maintained, responsive to the detection signals.

Claim 8

A data transfer rate deciding circuit, comprising: a receiver that separates data and a clock pulse from a received signal upon reception of a data transfer; a first generator that generates a first signal from the clock pulse, the first signal being synchronized with a reference frequency clock pulse; a second generator that generates a second signal responsive to the first signal; a first circuit that provides an exclusive-NOR value of the first signal and the second signal; a second circuit that detects whether or not the exclusive-NOR value is maintained at a low level, and that outputs responsive thereto a detection signal indicative of whether or not a data transfer rate of the received signal differs from a data transfer rate corresponding to the reference frequency clock pulse; and a determination circuit that outputs an error notification signal when the low level is not maintained, responsive to the detection signal.

Claim 9

A data transfer rate deciding circuit, comprising: a receiver that separates data and a clock pulse from a received signal upon reception of a data transfer; a first generator that generates a first signal from the clock pulse, the first signal being synchronized with a reference frequency clock pulse; a second generator that generates a second signal responsive to the first signal; a first circuit that provides an exclusive-NOR value of the first signal and the second signal; a second circuit that detects whether or not the exclusive-NOR value is maintained at a low level, and that outputs responsive thereto a detection signal indicative of whether or not a data transfer rate of the received signal differs from a data transfer rate corresponding to the reference frequency clock pulse; and a determination circuit that outputs an error notification signal when the low level is not maintained, responsive to the detection signal.

Claim 10

The data transfer rate deciding circuit of claim 6 , further comprising: an inverter that inverts the error notification signal to provide an inverted signal; and a logical AND gate that provides a logical AND value of a reference frequency and the inverted signal, as the reference frequency clock pulse.

Claim 11

The data transfer rate deciding circuit of claim 6 , further comprising: a counter that provides an excess notification signal when the error notification signal is output by the determination circuit in excess of a prescribed number of times.

Claim 12

The data transfer rate deciding circuit of claim 8 , wherein the prescribed number of times is set arbitrarily in the counter.

Claim 13

The data transfer rate deciding circuit of claim 8 , further comprising: an inverter that inverts the error notification signal to provide an inverted signal; and a logical AND gate that provides a logical AND value of a reference frequency and the inverted signal, as the reference frequency clock pulse.

Claim 14

The data transfer rate deciding circuit of claim 9 , further comprising: an inverter that inverts the error notification signal to provide an inverted signal; and a logical AND gate that provides a logical AND value of a reference frequency and the inverted signal, as the reference frequency clock pulse.

Claim 15

A data transfer rate deciding circuit comprising: a receiver that separates data and a clock pulse from a received signal upon reception of a data transfer; first generators that respectively generate first signals from the clock pulse, the first signals being respectively synchronized with reference frequency clock pulses of predetermined different frequencies; second generators that respectively generate respective second signals responsive to the first signals; first circuits that determine respective exclusive-NOR values of each of the first signals as taken with respect to the respective second signals; second circuits that respectively detect whether or not the exclusive-NOR values are maintained at low levels, and that output responsive thereto respective detection signals indicative of whether or not a data transfer rate of the received signal respectively differs from data transfer rates corresponding to the reference frequency clock pulses; and determination circuits that respectively output error notification signals when the low levels of the exclusive-NOR values are not maintained, responsive to the respective detection signals.

Claim 16

A data transfer rate deciding circuit comprising: a receiver that separates data and a clock pulse from a received signal upon reception of a data transfer; first generators that respectively generate first signals from the clock pulse, the first signals being respectively synchronized with reference frequency clock pulses of predetermined different frequencies; second generators that respectively generate respective second signals responsive to the first signals; first circuits that determine respective exclusive-NOR values of each of the first signals as taken with respect to the respective second signals; second circuits that respectively detect whether or not the exclusive-NOR values are maintained at low levels, and that output responsive thereto respective detection signals indicative of whether or not a data transfer rate of the received signal respectively differs from data transfer rates corresponding to the reference frequency clock pulses; and determination circuits that respectively output error notification signals when the low levels of the exclusive-NOR values are not maintained, responsive to the respective detection signals.

Claim 17

The data transfer deciding circuit of claim 12 , wherein when an error notification signal is output, at least a transfer rate deciding operation for each of the reference frequency clock pulses of the different frequencies for which an error notification signal has been output is stopped.