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US7274104B2 Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device having an interconnect that increases in impurity concentration as width increases

Assignee: Renesas Electronics Corp
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Filing: 2004-11-23
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Granted: 2007-09-25
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Expires: 2024-11-23
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Abstract

Abstract The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality of interconnect layers contains an impurity, and the wider the interconnect in the at least one interconnect layer is, the higher concentration of the impurity the interconnect contains.

Inventors

  • 👤 Toshiyuki Takewaki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 00:52
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/40; H10W20/41; H10W20/435; H10W20/44; H10W20/4403; H10W20/4421; H10W20/4424

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 117 words
A semiconductor device, comprising: a plurality of interconnect layers; wherein an interconnect in at least one interconnect layer among said plurality of interconnect layers contains an impurity; and as a width of said interconnect in said at least one interconnect layer increases, a concentration of said impurity in said interconnect increases, wherein said plurality of interconnect layers includes a lower interconnect layer including a shallow trench interconnect and an upper interconnect layer including a deep trench interconnect, said interconnect in said at least one interconnect layer among said plurality of interconnect layers is in said lower interconnect layer, and another interconnect in said upper interconnect layer is constituted of a metal that does not contain an impurity.
Claim 2
Dependent Claim 117 words
A semiconductor device, comprising: a plurality of interconnect layers; wherein an interconnect in at least one interconnect layer among said plurality of interconnect layers contains an impurity; and as a width of said interconnect in said at least one interconnect layer increases, a concentration of said impurity in said interconnect increases, wherein said plurality of interconnect layers includes a lower interconnect layer including a shallow trench interconnect and an upper interconnect layer including a deep trench interconnect, said interconnect in said at least one interconnect layer among said plurality of interconnect layers is in said lower interconnect layer, and another interconnect in said upper interconnect layer is constituted of a metal that does not contain an impurity.
Claim 3
Dependent Claim 51 words
The semiconductor device according to claim 1 , wherein said interconnect in said at least one interconnect layer among said plurality of interconnect layers includes a wide interconnect having a thickness thinner than a width thereof, and a narrow interconnect having a thickness equal to or greater than a width thereof.
Claim 4
Dependent Claim 24 words
The semiconductor device according to claim 2 , wherein said wide interconnect contains said impurity in a concentration of 0.1 to 10 atomic %.
Claim 5
Dependent Claim 31 words
The semiconductor device according to claim 1 , wherein said interconnect in said at least one interconnect layer among said plurality of interconnect layers is 400 nm or less in thickness.
Claim 6
Dependent Claim 43 words
The semiconductor device according to claim 1 , wherein the interconnect in said at least one interconnect layer among said plurality of interconnect layers is predominantly composed of copper, and said impurity is an element having a lower standard electrode potential than copper.

References Cited (Backward Citations)

JPH09289214A Cited
US6433402B1 Cited
US6943112B2 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2010-09-24 2011-03-26 2011-09-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2014-09-24 2015-03-26 2015-09-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2018-09-24 2019-03-26 2019-09-25 $7700.00 Window Closed / Lapsed

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