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US7274009B2 Expired / Lapsed US ⏱️ 0.0 years remaining

Frame-shuttered CMOS image sensor with simultaneous array readout

Assignee: Forza Silicon Corp
•
Filing: 2004-07-27
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Granted: 2007-09-25
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Expires: 2024-07-27
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Abstract

Abstract A frame shuttered CMOS image sensor with simultaneous array readout. An array of CMOS pixels are printed on a silicon substrate. Within each pixel is a light sensitive region comprising a photo sensitive diode for converting photons into electrical charge and at least three transistors to permit reading of reset electrical charges and collected electrical charges and for re-setting the photosensitive diode. The sensor includes an array of signal and re-set readout capacitors located on the substrate but outside of the pixel array. Metal conductors printed in said substrate connect each pixel in said pixel array with a signal capacitor and a re-set capacitor in array of signal and re-set readout capacitors. Transistor switches printed in said substrate but outside of said pixel array are used to isolate the signal and re-set capacitors from each other and from the pixels. Control circuitry is provided for re-setting simultaneously each of the pixels in the pixel array, for collecting simultaneously re-set signals from each pixel on to one of the reset capacitors in the array of readout capacitors and for collecting simultaneously integrated pixel signals from each pixel on to one of the signal capacitors in the array of readout capacitors. Readout circuitry is provided for reading charges collected on the array of signal and re-set capacitors.

Inventors

  • 👤 Steven Lei Huang
  • 👤 Daniel Alan Van Blerkom

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 13:16
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/50; H04N25/53; H04N25/531; H04N25/60; H04N25/616; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/18

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 272 words
A frame shuttered CMOS image sensor with simultaneous array readout comprising: A) an array of CMOS pixels printed on a silicon substrate, said array defining outside edges, with each pixel comprising: 1) a light sensitive region comprising a photo sensitive diode for converting photons into electrical charge, 2) at least three transistors to permit reading of collected electrical charge for re-setting said photosensitive diode at a re-set charge, and to permit reading of the re-set charge, B) an array of signal and re-set readout capacitors located on said substrate but outside of said pixel array but near at least one of the outside edges, said array of capacitors including one signal capacitor and one re-set readout capacitor for each pixel, C) a plurality of metal conductors printed in said substrate for connecting each pixel in said pixel array with a signal capacitor and a re-set capacitor in said array of signal and re-set readout capacitors, D) a plurality of transistor switches printed in said substrate but outside of said pixel array for isolating said signal and re-set capacitors from each other and from said pixels, E) control circuitry for re-setting simultaneously each of said pixels in said pixel array, for collecting simultaneously re-set signals from each pixel in said pixel array on one of the reset capacitors in said array of readout capacitors and for collecting simultaneously integrated pixel signals from each pixel in said pixel array on one of the signal capacitors in said array of readout capacitors, and F) readout circuitry for reading charges collected on said array of signal capacitors and said at least one array of re-set capacitors.
Claim 2
Dependent Claim 272 words
A frame shuttered CMOS image sensor with simultaneous array readout comprising: A) an array of CMOS pixels printed on a silicon substrate, said array defining outside edges, with each pixel comprising: 1) a light sensitive region comprising a photo sensitive diode for converting photons into electrical charge, 2) at least three transistors to permit reading of collected electrical charge for re-setting said photosensitive diode at a re-set charge, and to permit reading of the re-set charge, B) an array of signal and re-set readout capacitors located on said substrate but outside of said pixel array but near at least one of the outside edges, said array of capacitors including one signal capacitor and one re-set readout capacitor for each pixel, C) a plurality of metal conductors printed in said substrate for connecting each pixel in said pixel array with a signal capacitor and a re-set capacitor in said array of signal and re-set readout capacitors, D) a plurality of transistor switches printed in said substrate but outside of said pixel array for isolating said signal and re-set capacitors from each other and from said pixels, E) control circuitry for re-setting simultaneously each of said pixels in said pixel array, for collecting simultaneously re-set signals from each pixel in said pixel array on one of the reset capacitors in said array of readout capacitors and for collecting simultaneously integrated pixel signals from each pixel in said pixel array on one of the signal capacitors in said array of readout capacitors, and F) readout circuitry for reading charges collected on said array of signal capacitors and said at least one array of re-set capacitors.
Claim 3
Dependent Claim 42 words
The sensor as in claim 1 wherein said control circuitry comprises circuitry for storing reset values for the currently integrating frame on one of the two re-set capacitors and for storing the reset values for the previous frame on the other capacitor.
Claim 4
Dependent Claim 15 words
The sensor as in claim 1 wherein said pixel array comprises 156 or fewer pixels.
Claim 5
Dependent Claim 13 words
The sensor as in claim 1 wherein said pixel array comprises 64 pixels.
Claim 6
Dependent Claim 14 words
The sensor as in claim 1 wherein said pixel array comprises and 8.times.8 array.

References Cited (Backward Citations)

US5614744A Cited
US6803958B1 Cited
US6753912B1 Cited
US6917027B2 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2010-09-24 2011-03-26 2011-09-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2014-09-24 2015-03-26 2015-09-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2018-09-24 2019-03-26 2019-09-25 $7700.00 Window Closed / Lapsed

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