Patent US7199634B2 successfully refreshed from Google Patents.
US7199634B2
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US
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Duty cycle correction circuits suitable for use in delay-locked loops and methods of correcting duty cycles of periodic signals
Assignee: Samsung Electronics Co Ltd
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Filing: 2004-12-07
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Granted: 2007-04-03
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Expires: 2024-12-07
Abstract
Abstract Delay-locked loop integrated circuits include a duty cycle correction circuit. This duty cycle correction circuit generates at least one output clock signal having a substantially uniform duty cycle in response to at least one input clock signal having a non-uniform duty cycle. The duty cycle correction circuit is also responsive to a standby control signal that synchronizes timing of power-saving duty cycle update operations within the duty cycle correction circuit. These update operations reset the set point of the correction circuit.
Inventors
- 👤 Geun-hee Cho
- 👤 Kyu-hyoun Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:12
CPC Classifications
G; G11; G11C; G11C8/00; H; H03; H03K; H03K5/00; H03K5/15; H03K5/151; H03K5/13; H03K5/135; H03K5/156; H03K5/1565; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
175 words
An integrated circuit device, comprising: a duty cycle correction circuit configured to generate a complementary pair of output clock signals having substantially uniform duty cycles in response to a complementary pair of input clock signals having non-uniform duty cycles and a standby control signal that synchronizes timing of power-saving duty cycle update operations within said duty cycle correction circuit, said duty cycle correction circuit comprising: a duty cycle correction amplifier configured to generate the complementary pair of output clock signals in response to the complementary pair of input clock signals; a duty cycle detector configured to generate a complementary pair of pump output signals in response to the complementary pair of output clock signals; a comparator configured to generate a comparator output signal in response to the complementary pair of pump output signals; a counter configured to generate a digital output signal in response to the comparator output signal and the standby control signal; and a digital-to-analog converter configured to generate a complementary pair of analog output signals in response to the digital output signal.
Claim 2
Dependent Claim
175 words
An integrated circuit device, comprising: a duty cycle correction circuit configured to generate a complementary pair of output clock signals having substantially uniform duty cycles in response to a complementary pair of input clock signals having non-uniform duty cycles and a standby control signal that synchronizes timing of power-saving duty cycle update operations within said duty cycle correction circuit, said duty cycle correction circuit comprising: a duty cycle correction amplifier configured to generate the complementary pair of output clock signals in response to the complementary pair of input clock signals; a duty cycle detector configured to generate a complementary pair of pump output signals in response to the complementary pair of output clock signals; a comparator configured to generate a comparator output signal in response to the complementary pair of pump output signals; a counter configured to generate a digital output signal in response to the comparator output signal and the standby control signal; and a digital-to-analog converter configured to generate a complementary pair of analog output signals in response to the digital output signal.
Claim 3
Dependent Claim
30 words
The device of claim 1 , wherein said duty cycle correction circuit is responsive to the complementary pair of pump output signals and the complementary pair of analog output signals.
Claim 4
Dependent Claim
32 words
The device of claim 2 , further comprising a delay-locked loop configured to generate at least one of the complementary pair of input clock signals in response to an external clock signal.
Claim 5
Dependent Claim
187 words
An integrated circuit device, comprising: a duty cycle correction circuit configured to generate a complementary pair of output clock signals having substantially uniform duty cycles in response to a complementary pair of input clock signals having non-uniform duty cycles and support a power-saving mode of operation that temporarily stalls periodic switching of the complementary pair of output clock signals while a set point of the duty cycle correction circuit is updated, said duty cycle correction circuit comprising: a duty cycle correction amplifier configured to generate the complementary pair of output clock signals in response to the complementary pair of input clock signals; a duty cycle detector configured to generate a complementary pair of pump output signals in response to the complementary pair of output clock signals; a comparator configured to generate a comparator output signal in response to the complementary pair of pump output signals; a counter configured to generate a digital output signal in response to the comparator output signal and a standby control signal; and a digital-to-analog converter configured to generate a complementary pair of analog output signals in response to the digital output signal.
Claim 6
Dependent Claim
187 words
An integrated circuit device, comprising: a duty cycle correction circuit configured to generate a complementary pair of output clock signals having substantially uniform duty cycles in response to a complementary pair of input clock signals having non-uniform duty cycles and support a power-saving mode of operation that temporarily stalls periodic switching of the complementary pair of output clock signals while a set point of the duty cycle correction circuit is updated, said duty cycle correction circuit comprising: a duty cycle correction amplifier configured to generate the complementary pair of output clock signals in response to the complementary pair of input clock signals; a duty cycle detector configured to generate a complementary pair of pump output signals in response to the complementary pair of output clock signals; a comparator configured to generate a comparator output signal in response to the complementary pair of pump output signals; a counter configured to generate a digital output signal in response to the comparator output signal and a standby control signal; and a digital-to-analog converter configured to generate a complementary pair of analog output signals in response to the digital output signal.
Claim 7
Dependent Claim
30 words
The device of claim 4 , wherein said duty cycle correction circuit is responsive to the complementary pair of pump output signals and the complementary pair of analog output signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-04-02 | 2010-10-02 | 2011-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-04-02 | 2014-10-02 | 2015-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-04-02 | 2018-10-02 | 2019-04-03 | $7700.00 | Window Closed / Lapsed |