Patent US7149927B2 successfully refreshed from Google Patents.
US7149927B2
Expired / Lapsed
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Use of SMBus to provide JTAG support
Assignee: Hewlett Packard Development Co LP
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Filing: 2002-04-19
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Granted: 2006-12-12
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Expires: 2022-04-19
Abstract
Abstract An emulator is provided on an electronic assembly that permits external logic to communicate with test logic on the electronic assembly over an electrical interface that has fewer signals than the electrical interface associated with the test logic itself. In this way, external logic can communicate with test logic on the electronic assembly over an interface that uses fewer signal lines thereby permitting the electronic assembly's electrical connector to be smaller than it otherwise would be. In accordance with one embodiment, the test logic's interface comprises a JTAG interface having four signals (with an optional fifth signal) and the interface between the emulator and the external logic comprises a two wire SMBus communication link. In fact, the SMBus interface may already be provided to the electronic assembly for other reasons such as to provide control to and obtain status information from another component on said electronic assembly.
Inventors
- 👤 Charles J. Stancil
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:33
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F11/267; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318555
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
117 words
An electronic system, comprising: an electronic component comprising test logic; an emulator coupled to said test logic of said electronic component according to a first serial communication link; and a host test system coupled to said emulator according to a second serial communication link; wherein said first serial communication link is in accordance with a different communication protocol than said second communication link and said emulator converts communications between said first and second serial communication links; and wherein said emulator receives a communication packet from the host test system, said packet comprising a data value including a control field which encodes the number of serial data bits the emulator is to serially transmit to the test logic.
Claim 2
Dependent Claim
117 words
An electronic system, comprising: an electronic component comprising test logic; an emulator coupled to said test logic of said electronic component according to a first serial communication link; and a host test system coupled to said emulator according to a second serial communication link; wherein said first serial communication link is in accordance with a different communication protocol than said second communication link and said emulator converts communications between said first and second serial communication links; and wherein said emulator receives a communication packet from the host test system, said packet comprising a data value including a control field which encodes the number of serial data bits the emulator is to serially transmit to the test logic.
Claim 3
Dependent Claim
15 words
The system of claim 1 wherein said first serial communication link comprises a JTAG bus.
Claim 4
Dependent Claim
15 words
The system of claim 2 wherein said second serial communication link comprises an SMBus link.
Claim 5
Dependent Claim
15 words
The system of claim 1 wherein said second serial communication link comprises an SMBus link.
Claim 6
Dependent Claim
15 words
The system of claim 4 wherein said first serial communication link comprises a JTAG bus.
Claim 7
Dependent Claim
34 words
The system of claim 1 wherein said emulator receives communication packets from said host test system, said communication packets encoding information to be provided to said test logic over said first serial communication link.
Claim 8
Dependent Claim
21 words
The system of claim 1 wherein said packet also includes the serial data bits to be provided to the test logic.
Claim 9
Dependent Claim
39 words
The system of claim 7 wherein said emulator reads said control field and provides each of said serial data bits to said test logic on successive clock pulses of a clock signal coupling said emulator and said test logic.
Claim 10
Dependent Claim
30 words
The system of claim 1 wherein said packet also includes a mode bit to be provided to the test logic which effects the mode of operation of the test logic.
Claim 11
Dependent Claim
27 words
The system of claim 1 wherein said control field also encodes an indication of whether the emulator is to assert a reset signal to said test logic.
Claim 12
Dependent Claim
22 words
The system of claim 10 wherein said emulator deasserts said reset signal a predetermined period of time after asserting the reset signal.
Claim 13
Dependent Claim
50 words
The system of claim 10 wherein said host system causes said reset signal to be deasserted by issuing a command to said emulator over said second communication link which includes a value in said control field that is different than the value which caused the reset signal to be asserted.
Claim 14
Dependent Claim
98 words
An electronic system, comprising: an electronic component comprising test logic used to test said electronic component, said test logic accessible by a first electrical interface comprising m signals; and an emulator coupled to said test logic using via said first electrical interface, said emulator providing a second electrical interface to external logic via a second electrical interface comprising n signals; wherein n is less than m; and wherein said emulator receives a data value from the external logic, said data value encoding the number of serial data bits the emulator is to serially transmit to the test logic.
Claim 15
Dependent Claim
98 words
An electronic system, comprising: an electronic component comprising test logic used to test said electronic component, said test logic accessible by a first electrical interface comprising m signals; and an emulator coupled to said test logic using via said first electrical interface, said emulator providing a second electrical interface to external logic via a second electrical interface comprising n signals; wherein n is less than m; and wherein said emulator receives a data value from the external logic, said data value encoding the number of serial data bits the emulator is to serially transmit to the test logic.
Claim 16
Dependent Claim
14 words
The system of claim 13 wherein said first electrical interface comprises a JTAG bus.
Claim 17
Dependent Claim
14 words
The system of claim 14 wherein said second electrical interface comprises an SMBus link.
Claim 18
Dependent Claim
14 words
The system of claim 13 wherein said second electrical interface comprises an SMBus link.
Claim 19
Dependent Claim
14 words
The system of claim 15 wherein said first electrical interface comprises a JTAG bus.
Claim 20
Dependent Claim
33 words
The system of claim 13 wherein said emulator receives communication packets from said host test system, said communication packets encoding information to be provided to said test logic over said first electrical interface.
Claim 21
Dependent Claim
21 words
The system of claim 13 wherein said packet also includes the serial data bits to be provided to the test logic.
Claim 22
Dependent Claim
39 words
The system of claim 19 wherein said emulator reads said control field and provides each of said serial data bits to said test logic on successive clock pulses of a clock signal coupling said emulator and said test logic.
Claim 23
Dependent Claim
30 words
The system of claim 13 wherein said packet also includes a mode bit to be provided to the test logic which effects the mode of operation of the test logic.
Claim 24
Dependent Claim
27 words
The system of claim 13 wherein said control field also encodes an indication of whether the emulator is to assert a reset signal to said test logic.
Claim 25
Independent Claim
80 words
A method of communicating with test logic on an electronic component; (a) providing a communication packet to a bridge which couples to the test logic in said electronic component; (b) decoding said communication packet to extract a control field value which encodes the number of test data bits contained in the packet; (c) decoding said communication packet to extract the test data bits provided therein; and (d) outputting a serial stream of the test data bits to said test logic.
Claim 26
Independent Claim
80 words
A method of communicating with test logic on an electronic component; (a) providing a communication packet to a bridge which couples to the test logic in said electronic component; (b) decoding said communication packet to extract a control field value which encodes the number of test data bits contained in the packet; (c) decoding said communication packet to extract the test data bits provided therein; and (d) outputting a serial stream of the test data bits to said test logic.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-12-11 | 2010-06-12 | 2010-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-12-11 | 2014-06-12 | 2014-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-12-11 | 2018-06-12 | 2018-12-12 | $7700.00 | Window Closed / Lapsed |