Duty cycle correction circuit of delay locked loop and the delay locked loop having the duty cycle correction circuit

Claim 2

A duty cycle correction circuit of, comprising: a differential amplifier, which receives and amplifies differential reference clock signals through a first input terminal and a second input terminal, and outputs differential output signals to a first differential output terminal and a second differential output terminal, respectively; a first transmission circuit, which is connected between the first differential output terminal and a first node, and transmits a signal of the first differential output terminal to the first node, in response to transmission control signals; a second transmission circuit, which is connected between the second differential output terminal and a second node, and transmits a signal of the second differential output terminal to the second node, in response to the transmission control signals; a first storage unit, which is connected between the first node and a ground voltage and accumulates electric charges on the first node; a second storage unit, which is connected between the second node and the ground voltage and accumulates electric charges on the second node; and a current control circuit, which controls an amount of electric charges accumulated in the first storage unit and an amount of electric charges accumulated in the second storage unit, in response to a combination of duty cycle switching signals and corresponding current switching control signals.

Claim 3

The duty cycle correction circuit of claim 1 , wherein each of the first transmission circuit and the second transmission circuit is a transmission gate.

Claim 4

The duty cycle correction circuit of claim 1 , wherein each of the first storage unit and the second storage unit is a MOS transistor.

Claim 5

The duty cycle correction circuit of claim 1 , wherein the duty cycle switching signals comprise a duty cycle reduction signal and a duty cycle enhancement signal.

Claim 6

The duty cycle correction circuit of claim 6 , wherein one of the duty cycle reduction signal and the duty cycle enhancement signal is activated at one time.

Claim 7

The duty cycle correction circuit of claim 6 , wherein a combination of the duty cycle reduction signal and at least one active corresponding switching control signal reduces the amount of electric charges accumulated in the first storage unit.

Claim 8

A delay locked loop comprising: the duty cycle correction circuit of claim 1 .

Claim 9

The delay locked loop of claim 7 further comprising: a DLL core, which receives an external clock signal and generates an internal clock signal synchronized to the external clock signal; a buffer, which buffers the internal clock signal and outputs the differential reference clock signals; and a control signal generation circuit, which generates the combination of duty cycle switching signals and corresponding current switching control signals for controlling a predetermined offset, and outputs the combination of the duty cycle switching signals and corresponding current switching control signals to the duty cycle correction circuit, wherein the duty cycle correction circuit generates duty rate control signals each having the predetermined offset corresponding to a difference of respective duty cycles of the differential reference clock signals and the DLL core corrects a duty cycle of the internal clock signal, in response to the duty rate control signals.

Claim 10

A delay locked loop comprising: a DLL core, which receives an external clock signal and generates an internal clock signal synchronized to the external clock signal; a buffer, which buffers the internal clock signal and outputs differential reference clock signals; and a duty cycle correction circuit, which generates duty rate control signals each having a predetermined offset corresponding to a difference of respective duty cycles of the differential reference clock signals, the duty cycle correction circuit comprising: a differential amplifier, which receives and amplifies differential reference clock signals through a first input terminal and a second input terminal, and outputs differential output signals to a first differential output terminal and a second differential output terminal, respectively; a first transmission circuit, which is connected between the first differential output terminal and a first node, and transmits a signal of the first differential output terminal to the first node, in response to transmission control signals; a second transmission circuit, which is connected between the second differential output terminal to the second node, in response to the transmission control signals; a first storage unit, which is connected between the first node and a ground voltage and accumulates electric charges on the first node; a second storage unit, which is connected between the second node and the ground voltage and accumulates electric charges on the second node; and a current control circuit, which controls an amount of electric charges accumulated in the first storage unit and an amount of electric charges accumulated in the second storage unit, in response to a combination of duty cycle switching signals and corresponding current switching control signals; and a control signal generation circuit, which generates the combination of duty cycle switching signals and corresponding current switching control signals for controlling the offset, and outputs the combination of the duty cycle switching signals and corresponding current switching control signals to the duty cycle correction circuit, wherein the DLL core corrects a duty cycle of the internal clock signal, in response to the duty rate control signals.

Claim 11

A delay locked loop comprising: a DLL core, which receives an external clock signal and generates an internal clock signal synchronized to the external clock signal; a buffer, which buffers the internal clock signal and outputs differential reference clock signals; and a duty cycle correction circuit, which generates duty rate control signals each having a predetermined offset corresponding to a difference of respective duty cycles of the differential reference clock signals, the duty cycle correction circuit comprising: a differential amplifier, which receives and amplifies differential reference clock signals through a first input terminal and a second input terminal, and outputs differential output signals to a first differential output terminal and a second differential output terminal, respectively; a first transmission circuit, which is connected between the first differential output terminal and a first node, and transmits a signal of the first differential output terminal to the first node, in response to transmission control signals; a second transmission circuit, which is connected between the second differential output terminal to the second node, in response to the transmission control signals; a first storage unit, which is connected between the first node and a ground voltage and accumulates electric charges on the first node; a second storage unit, which is connected between the second node and the ground voltage and accumulates electric charges on the second node; and a current control circuit, which controls an amount of electric charges accumulated in the first storage unit and an amount of electric charges accumulated in the second storage unit, in response to a combination of duty cycle switching signals and corresponding current switching control signals; and a control signal generation circuit, which generates the combination of duty cycle switching signals and corresponding current switching control signals for controlling the offset, and outputs the combination of the duty cycle switching signals and corresponding current switching control signals to the duty cycle correction circuit, wherein the DLL core corrects a duty cycle of the internal clock signal, in response to the duty rate control signals.