Patent AT164975B successfully refreshed from Google Patents.
Patent US7109750B2 successfully refreshed from Google Patents.
US7109750B2
Expired / Lapsed
US
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Reconfiguration port for dynamic reconfiguration-controller
Assignee: Xilinx Inc
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Filing: 2004-04-30
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Granted: 2006-09-19
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Expires: 2024-04-30
Abstract
Abstract Method and apparatus for a controller for dynamic configuration is described. The controller comprises a port interface, a read/write interface, and a plurality of flip-flops. The flip-flops, couple the port interface to the read/write interface. The port interface is configured to receive a plurality of signals, where portion of the plurality of signals are pipelined through the plurality of flip-flops responsive to a data clock signal of the plurality of signals. This facilitates reading and writing to storage elements at a rate which is at least approximately a frequency of the data clock signal while operating a device at approximately such frequency in which the controller is instantiated.
Inventors
- 👤 Vasisht Mantra Vadi
- 👤 David P. Schultz
- 👤 John D. Logue
- 👤 John McGrath
- 👤 Anthony Collins
- 👤 F. Erich Goetting
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
86 words
A controller in a programmable logic device, the controller comprising: a port interface; a read/write interface; a plurality of flip-flops coupling the port interface to the read/write interface; the port interface configured to receive a plurality of signals; wherein the plurality of signals comprise a data input signal, a data address signal, a data write signal and a data activate signal; and a portion of the plurality of signals pipelined through the plurality of flip-flops responsive to a data clock signal of the plurality of signals.
Claim 2
Dependent Claim
86 words
A controller in a programmable logic device, the controller comprising: a port interface; a read/write interface; a plurality of flip-flops coupling the port interface to the read/write interface; the port interface configured to receive a plurality of signals; wherein the plurality of signals comprise a data input signal, a data address signal, a data write signal and a data activate signal; and a portion of the plurality of signals pipelined through the plurality of flip-flops responsive to a data clock signal of the plurality of signals.
Claim 3
Dependent Claim
72 words
The controller, according to claim 1 , wherein each flip-flop of the plurality of flip-flops is coupled to receive a respective one of the data input signal, the data address signal, the data write signal and the data activate signal and configured to respectively clock out pipelined versions of the data input signal, the data address signal, the data write signal and the data activate signal responsive to the data clock signal.
Claim 4
Dependent Claim
39 words
The controller, according to claim 2 , wherein a pipelined version of the data write signal, a pipelined version of the data activate signal, and the data clock signal are provided to combinational logic to provide a write signal.
Claim 5
Dependent Claim
38 words
The controller, according to claim 3 , wherein the controller is configured to transfer control from signaling on the port interface to piped signaling on the read/write interface responsive to a rising edge of the data clock signal.
Claim 6
Dependent Claim
40 words
The controller, according to claim 4 , wherein the controller is configured to change state to a write active state responsive to a falling edge of the data clock signal immediately following the rising edge of the data clock signal.
Claim 7
Dependent Claim
44 words
The controller, according to claim 5 , wherein the controller is configured to change state to a write inactive state responsive to another rising edge of the data clock signal, the other rising edge immediately following the falling edge of the data clock signal.
Claim 8
Dependent Claim
25 words
The controller, according to claim 6 , wherein the plurality of flip-flops are all clocked on a same clock cycle of the data clock signal.
Claim 9
Dependent Claim
29 words
The controller, according to claim 7 , wherein the plurality of flip-flops are all clocked on a leading edge of the same clock cycle of the data clock signal.
Claim 10
Dependent Claim
34 words
The controller, according to claim 2 , wherein pipelined versions of the date activate signal and the data address signal are provided as inputs to combinational logic to provide a data activate ready signal.
Claim 11
Dependent Claim
46 words
The controller, according to claim 9 , further comprising another plurality of flip-flops, the other plurality of flip-flops coupled in series and coupled to receive the data activate ready signal as a data input, the other plurality of flip-flops clocked responsive to the data clock signal.
Claim 12
Dependent Claim
20 words
The controller, according to claim 10 , wherein output from the other plurality of flip-flops is a data ready signal.
Claim 13
Dependent Claim
34 words
The controller, according to claim 11 , wherein the port interface is configured to output another plurality of signals, the other plurality of signals including a data output signal and the data ready signal.
Claim 14
Dependent Claim
41 words
The controller, according to claim 10 , wherein output from the other plurality of flip-flops is provided as input to combinational logic along with a function block logic control signal, the output of the combination logic being a data ready signal.
Claim 15
Dependent Claim
34 words
The controller, according to claim 13 , wherein the port interface is configured to output another plurality of signals, the other plurality of signals including a data output signal and the data ready signal.
Claim 16
Dependent Claim
26 words
The controller, according to claim 2 , further comprising selection circuitry coupled to receive a read port signal and a status port signal as data inputs.
Claim 17
Dependent Claim
29 words
The controller, according to claim 15 , wherein the selection circuitry is configured to select a data output signal responsive to a pipelined version of the data address signal.
Claim 18
Dependent Claim
17 words
The controller, according to claim 16 , wherein the data output signal comprises data read from memory.
Claim 19
Dependent Claim
18 words
The controller, according to claim 16 , wherein the data output signal comprises data read from status registers.
Claim 20
Dependent Claim
45 words
The controller, according to claim 3 , further comprising a plurality of coordinate-to-address converters coupled to receive the write signal and coordinate signals, the plurality of coordinate-to-address converters configured to provide read and write address signals responsive to the write signal and the coordinate signals.
Claim 21
Dependent Claim
37 words
The controller, according to claim 19 , further comprising a decoder, the decoder coupled to receive address information from the pipelined version of the data address signal and to provide a coordinate signal of the coordinate signals.
Claim 22
Dependent Claim
19 words
The controller, according to claim 20 , wherein the coordinate signals are for addressing an array of memory cells.
Claim 23
Independent Claim
121 words
A method for dynamic configuration of function block logic, comprising: receiving a data clock signal, a data write signal, a data activation signal, a data address signal, and a data input signal; pipelining the data write signal, the data activation signal, the data address signal and the data input signal responsive to the data clock signal to provide pipelined versions of the data write signal, the data activation signal, the data address signal and the data input signal; and writing to storage elements responsive to the pipelined versions of the data write signal, the data activation signal, the data address signal and the data input signal at a rate which is at least approximately a frequency of the data clock signal.
Claim 24
Independent Claim
121 words
A method for dynamic configuration of function block logic, comprising: receiving a data clock signal, a data write signal, a data activation signal, a data address signal, and a data input signal; pipelining the data write signal, the data activation signal, the data address signal and the data input signal responsive to the data clock signal to provide pipelined versions of the data write signal, the data activation signal, the data address signal and the data input signal; and writing to storage elements responsive to the pipelined versions of the data write signal, the data activation signal, the data address signal and the data input signal at a rate which is at least approximately a frequency of the data clock signal.
Claim 25
Dependent Claim
21 words
The method, according to claim 22 , wherein data obtained from the data input signal is written to the storage elements.
Claim 26
Dependent Claim
14 words
The method, according to claim 23 , wherein the storage elements are memory cells.
Claim 27
Dependent Claim
13 words
The method, according to claim 23 , wherein the storage elements are registers.
Claim 28
Dependent Claim
16 words
The method, according to claim 22 , wherein the frequency is at least approximately 500 MHz.
Claim 29
Dependent Claim
20 words
The method, according to claim 26 , wherein the writing takes place during a same clock cycle as the pipelining.
Claim 30
Dependent Claim
22 words
The method, according to claim 27 , wherein the writing takes place once clock cycle after a clock cycle of the pipelining.
Claim 31
Independent Claim
130 words
An apparatus for dynamic configuration of function block logic, comprising: receiving means for receiving a data clock signal, a data write signal, a data activation signal, a data address signal, and a data input signal; pipelining means for pipelining the data write signal, the data activation signal, the data address signal and the data input signal responsive to the data clock signal to provide pipelined versions of the data write signal, the data activation signal, the data address signal and the data input signal; and writing means for writing to storage elements responsive to the pipelined versions of the data write signal, the data activation signal, the data address signal and the data input signal at a rate which is at least approximately a frequency of the data clock signal.
Claim 32
Independent Claim
130 words
An apparatus for dynamic configuration of function block logic, comprising: receiving means for receiving a data clock signal, a data write signal, a data activation signal, a data address signal, and a data input signal; pipelining means for pipelining the data write signal, the data activation signal, the data address signal and the data input signal responsive to the data clock signal to provide pipelined versions of the data write signal, the data activation signal, the data address signal and the data input signal; and writing means for writing to storage elements responsive to the pipelined versions of the data write signal, the data activation signal, the data address signal and the data input signal at a rate which is at least approximately a frequency of the data clock signal.
Claim 33
Independent Claim
89 words
A method for dynamic configuration of function block logic, comprising: receiving a data clock signal, a data activation signal and a data address signal; pipelining the data activation signal and the data address signal responsive to the data clock signal to provide pipelined versions of the data activation signal and the data address signal; and reading from storage elements responsive to the pipelined versions of the data activation signal and the data address signal at a rate which is at least approximately a frequency of the data clock signal.
Claim 34
Independent Claim
89 words
A method for dynamic configuration of function block logic, comprising: receiving a data clock signal, a data activation signal and a data address signal; pipelining the data activation signal and the data address signal responsive to the data clock signal to provide pipelined versions of the data activation signal and the data address signal; and reading from storage elements responsive to the pipelined versions of the data activation signal and the data address signal at a rate which is at least approximately a frequency of the data clock signal.
Claim 35
Dependent Claim
14 words
The method, according to claim 30 , wherein the storage elements are memory cells.
Claim 36
Dependent Claim
13 words
The method, according to claim 30 , wherein the storage elements are registers.
Claim 37
Dependent Claim
16 words
The method, according to claim 30 , wherein the frequency is at least approximately 500 MHz.
Claim 38
Dependent Claim
26 words
The method, according to claim 32 , wherein the reading takes place by at least a second clock cycle after a clock cycle of the pipelining.
Claim 39
Independent Claim
98 words
An apparatus for dynamic configuration of function block logic, comprising: receiving means for receiving a data clock signal, a data activation signal and a data address signal; pipelining means for pipelining the data activation signal and the data address signal responsive to the data clock signal to provide pipelined versions of the data activation signal and the data address signal; and reading means for reading from storage elements responsive to the pipelined versions of the data activation signal and the data address signal at a rate which is at least approximately a frequency of the data clock signal.
Claim 40
Independent Claim
98 words
An apparatus for dynamic configuration of function block logic, comprising: receiving means for receiving a data clock signal, a data activation signal and a data address signal; pipelining means for pipelining the data activation signal and the data address signal responsive to the data clock signal to provide pipelined versions of the data activation signal and the data address signal; and reading means for reading from storage elements responsive to the pipelined versions of the data activation signal and the data address signal at a rate which is at least approximately a frequency of the data clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-09-18 | 2010-03-20 | 2010-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-09-18 | 2014-03-20 | 2014-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-09-18 | 2018-03-20 | 2018-09-19 | $7700.00 | Window Closed / Lapsed |