Patent US7089140B1 successfully refreshed from Google Patents.
US7089140B1
Expired / Lapsed
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Programmable logic device and method of testing a programmable logic device
Assignee: Altera Corp
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Filing: 2004-08-20
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Granted: 2006-08-08
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Expires: 2024-08-20
Abstract
Abstract A programmable logic device includes a functional block, which does not form part of an embedded processor, which can perform a testing function on other functional blocks of the programmable logic device. Thus, the test block can read stored data values from registers in the other functional blocks of the programmable logic device, or can read signal values at points in the other functional blocks of the programmable logic device, or can insert specific data values in registers in the other functional blocks of the programmable logic device.
Inventors
- 👤 Graham McKenzie
- 👤 Joel A. Seely
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:09
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
133 words
A programmable logic device, comprising: a plurality of functional blocks; an interface for connection to an external computer system; a test block, wherein the test block is separate from any processor implemented in the programmable logic device, and wherein the test block is able to receive commands received from the external computer system via said interface, and wherein, in response to commands received from the external computer system via said interface, said test block is able to monitor operation of said functional blocks; and a bus, for interconnecting said plurality of functional blocks and said test block, wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a bus master to control at least one of said plurality of functional blocks.
Claim 2
Dependent Claim
133 words
A programmable logic device, comprising: a plurality of functional blocks; an interface for connection to an external computer system; a test block, wherein the test block is separate from any processor implemented in the programmable logic device, and wherein the test block is able to receive commands received from the external computer system via said interface, and wherein, in response to commands received from the external computer system via said interface, said test block is able to monitor operation of said functional blocks; and a bus, for interconnecting said plurality of functional blocks and said test block, wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a bus master to control at least one of said plurality of functional blocks.
Claim 3
Dependent Claim
24 words
A programmable logic device as claimed in claim 1 , wherein said interface for connection to an external computer system is a JTAG interface.
Claim 4
Dependent Claim
57 words
A programmable logic device as claimed in claim 1 , wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a bus master to read the value of a signal appearing at least one location in at least one of said plurality of functional block.
Claim 5
Dependent Claim
55 words
A programmable logic device as claimed in claim 1 , wherein, a response to commands received from the external computer system via said interface, said test block is able to act as a bus master to read a value stored in at least one register in at least one of said plurality of functional blocks.
Claim 6
Dependent Claim
50 words
A programmable logic device as claimed in claim 1 , wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a bus master to read a value stored in at least one memory of the programmable logic device.
Claim 7
Dependent Claim
55 words
A programmable logic device as claimed in claim 1 , wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a bus master to store a desired value in at least one register in at least one of said plurality of functional blocks.
Claim 8
Dependent Claim
50 words
A programmable logic device as claimed in claim 1 , wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a bus master to store a desired value in at least one memory of the programmable logic device.
Claim 9
Dependent Claim
179 words
A computer system, comprising: a computer system, running a test software product; and a programmable logic device, wherein said programmable logic device comprises: a plurality of functional blocks; an interface for connection to an external computer system; a test block, wherein the test block is separate from any processor implemented in the programmable logic device, wherein, in response to user inputs, said computer system is able to generate commands to be sent to the programmable logic device, and wherein the test block of the programmable logic device is able to receive said commands received from the external computer system via said interface, and, in response to said commands received from the external computer system via said interface, said test block is able to monitor operation of said functional blocks; and a bus, for interconnecting said plurality of functional blocks and said test block, wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a bus master to control at least one of said plurality of functional blocks.
Claim 10
Dependent Claim
179 words
A computer system, comprising: a computer system, running a test software product; and a programmable logic device, wherein said programmable logic device comprises: a plurality of functional blocks; an interface for connection to an external computer system; a test block, wherein the test block is separate from any processor implemented in the programmable logic device, wherein, in response to user inputs, said computer system is able to generate commands to be sent to the programmable logic device, and wherein the test block of the programmable logic device is able to receive said commands received from the external computer system via said interface, and, in response to said commands received from the external computer system via said interface, said test block is able to monitor operation of said functional blocks; and a bus, for interconnecting said plurality of functional blocks and said test block, wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a bus master to control at least one of said plurality of functional blocks.
Claim 11
Independent Claim
123 words
A method of testing a programmable logic device comprising a plurality of functional blocks, the method comprising: generating a command in an external computer system; transmitting said command from said external computer system to said programmable logic device; and in a test block of said programmable logic device, wherein the test block is separate from any processor implemented in the programmable logic device, translating said command such that said test block is able to monitor operation of said functional blocks, wherein said test block of said programmable logic device is connected to said plurality of functional blocks by means of a bus, and wherein said step of translating said command comprises causing said test block to act as a master on said bus.
Claim 12
Independent Claim
123 words
A method of testing a programmable logic device comprising a plurality of functional blocks, the method comprising: generating a command in an external computer system; transmitting said command from said external computer system to said programmable logic device; and in a test block of said programmable logic device, wherein the test block is separate from any processor implemented in the programmable logic device, translating said command such that said test block is able to monitor operation of said functional blocks, wherein said test block of said programmable logic device is connected to said plurality of functional blocks by means of a bus, and wherein said step of translating said command comprises causing said test block to act as a master on said bus.
Claim 13
Dependent Claim
43 words
A method as claimed in claim 9 , wherein said test block is able to act as a bus master to read the value of a signal appearing at at least one location in at least one of said plurality of functional blocks.
Claim 14
Dependent Claim
40 words
A method as claimed in claim 9 , wherein said test block is able to act as a bus master to read a value stored in at least one register in at least one of said plurality of functional blocks.
Claim 15
Dependent Claim
40 words
A method as claimed in claim 9 , wherein said test block is able to act as a bus master to store a desired value in at least one register in at least one of said plurality of functional blocks.
Claim 16
Dependent Claim
118 words
A programmable logic device, comprising: a plurality of functional blocks; at least one bus, for interconnecting said plurality of functional blocks; an interface, for connection to an external computer system; and a test block, connected to said bus and to said interface, wherein said test block is not able to act as a general purpose microprocessor, and wherein the test block is able to receive commands received from the external computer system via said interface, and wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a master on said bus to transmit data to said functional blocks, and to request data from said functional blocks.
Claim 17
Dependent Claim
118 words
A programmable logic device, comprising: a plurality of functional blocks; at least one bus, for interconnecting said plurality of functional blocks; an interface, for connection to an external computer system; and a test block, connected to said bus and to said interface, wherein said test block is not able to act as a general purpose microprocessor, and wherein the test block is able to receive commands received from the external computer system via said interface, and wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a master on said bus to transmit data to said functional blocks, and to request data from said functional blocks.
Claim 18
Dependent Claim
113 words
A programmable logic device, comprising: a plurality of functional blocks; at least one bus, for interconnecting said plurality of functional blocks; an interface, for connection to an external computer system; and a test block, connected to said bus and to said interface, wherein the test block is able to perform a testing function by receiving commands from the external computer system via said interface, and, in response to commands received from the external computer system via said interface, by acting as a master on said bus to transmit data to said functional blocks, and to request data from said functional blocks, wherein said testing function is the sole function of said test block.
Claim 19
Dependent Claim
113 words
A programmable logic device, comprising: a plurality of functional blocks; at least one bus, for interconnecting said plurality of functional blocks; an interface, for connection to an external computer system; and a test block, connected to said bus and to said interface, wherein the test block is able to perform a testing function by receiving commands from the external computer system via said interface, and, in response to commands received from the external computer system via said interface, by acting as a master on said bus to transmit data to said functional blocks, and to request data from said functional blocks, wherein said testing function is the sole function of said test block.
Claim 20
Dependent Claim
119 words
A programmable logic device, comprising: a plurality of functional blocks; at least one bus, for interconnecting said plurality of functional blocks; an interface, for connection to an external computer system; and a test block, connected to said bus and to said interface, wherein said test block uses significantly fewer programmable logic resources than a general purpose microprocessor, and wherein the test block is able to receive commands received form the external computer system via said interface, and wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a master on said bus to transmit data to said functional blocks, and to request data from said functional blocks.
Claim 21
Dependent Claim
119 words
A programmable logic device, comprising: a plurality of functional blocks; at least one bus, for interconnecting said plurality of functional blocks; an interface, for connection to an external computer system; and a test block, connected to said bus and to said interface, wherein said test block uses significantly fewer programmable logic resources than a general purpose microprocessor, and wherein the test block is able to receive commands received form the external computer system via said interface, and wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a master on said bus to transmit data to said functional blocks, and to request data from said functional blocks.
Claim 22
Dependent Claim
127 words
A programmable logic device, comprising: a plurality of functional blocks; a processor capable of monitoring operation of said functional blocks; an interface for connection to an external computer system; a test block, wherein the test block is able to receive commands received from the external computer system via said interface, and wherein, in response to commands received from the external computer system via said interface, said test block is able to monitor operation of said functional blocks; and a bus, for interconnecting said plurality of functional blocks and said test block, wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a bus master to control at least one of said plurality of functional blocks.
Claim 23
Dependent Claim
127 words
A programmable logic device, comprising: a plurality of functional blocks; a processor capable of monitoring operation of said functional blocks; an interface for connection to an external computer system; a test block, wherein the test block is able to receive commands received from the external computer system via said interface, and wherein, in response to commands received from the external computer system via said interface, said test block is able to monitor operation of said functional blocks; and a bus, for interconnecting said plurality of functional blocks and said test block, wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a bus master to control at least one of said plurality of functional blocks.
Claim 24
Dependent Claim
57 words
A programmable logic device as claimed in claim 16 , wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a bus master to read the value of a signal appearing at least one location in at least one of said plurality of functional block.
Claim 25
Dependent Claim
55 words
A programmable logic device as claimed in claim 16 , wherein, in response to commands received from the external computer system via said interface, said test block is able to act as a bus master to store a desired value in at least one register in at least one of said plurality of functional blocks.
References Cited (Backward Citations)
US6704889B2
Cited
US20040098638A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-08-07 | 2010-02-06 | 2010-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-08-07 | 2014-02-06 | 2014-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-08-07 | 2018-02-06 | 2018-08-08 | $7700.00 | Window Closed / Lapsed |